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| 型号： | R0K436079S000BE |
| 厂商： | Renesas Electronics America |
| 文件页数： | 10/50页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR H8/36079 W/COMPILER |
| 产品培训模块： | Electromagnetic Noise Reduction Techniques Part 1 |
| 标准包装： | 1 |
| 系列： | H8® |
| 类型： | MCU |
| 适用于相关产品： | H8/36079 |
| 所含物品： | 评估板 |
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H8 Family — On-chip Peripherals: Communication I/F
?
■ Ethernet Hardware MAC 100/10
8
? Transmission and reception of
Ethernet/IEEE802.3 frames
E-DMAC
De s criptor
Tran s mit
FIFO
MAC
Receive
controller
Tran s mit
controller
? Supports 10/100 Mbps receive/transfer
? Supports full-duplex and half-duplex modes
? Conforms to IEEE802.3u standard MII
(Media Independent Interface)
information
Tran s mit
DMAC
De s criptor
information
Receive
FIFO
Command
s tatu s
interface
MII
? Ma g ic P acket detection and
Wake-On-LAN (WOL) si g nal output
? Conforms to IEEE802.3x flow control
? D edicated E- D MAC ( D MA Controller)
RAM
Tran s mit
Receive
DMAC
Converter
MII/RMII conver s ion
PORT
? Transmit/receive frame status information
de s criptor
Tran s mit
buffer
PHY
is indicated in descriptors
Receive
? Achieves efficient system bus utilization
throu g h use of block transfer (16-byte units)
? Supports sin g le-frame/multi-buffer operation
de s criptor
Receive
buffer
Ethernet Hardware
MAC 100/10
Block Diagram
■ Univer s al S erial Bu s
? P rovides v2.0 support
USB
1280-Byte FIFO
EP0 s EP0o
EP0i EP1i
EP2i
EP2o
EP3i
EP3o
EP4i
EP4o
EP5i
[Power mode s election]
UBPM
[Connection/di s connection]
VBUS
? Offers full-speed, 12Mbps
IRQ6
[Interrupt reque s t s ignal]
[Su s pend]
USPND
communication
? Bus-powered mode or
self-powered
EXIRQ0, EXIRQ1
DREQ0, DREQ1
[Internal bu s ]
Peripheral data bu s
Peripheral addre ss bu s
Peripheral bu s
[DMA internal reque s t s ignal]
Interface
Regi s ter s
Internal
tran s ceiver
[Power s upply]
DrVcc
DrV ss
[Data]
USD+ R s D+
USD- R s D-
? Up to 9 endpoints can be specified
? Four transfer modes supported:
control s ignal
UDC s ynchronization
circuit
Legend:
UDC:
USB Device Controller
Control, Interrupt, Bulk,
and Isochronous
? On-chip bus transceiver with
[Sy s tem clock]
φ
(16MHz)
[USB operating clock]
EXTAL48
PLL circuit (48MHz)
(x3)
USB clock
(12MHz)
UDC core
EP0s:
Endpoint 0 s etup FIFO
EP0i to 5i:
Endpoint 0 to 5 In FIFO
EP0o to 4o:
option for usin g external transceiver
XTAL48
generator
(48MHz)
Endpoint 0 to 4 Out FIFO
? Total 1280-Byte FIFO buffer
■ Controller Area Networ k (RCAN-ET)
CAN interface
USB Block Diagram: H8S/2215R
? Supports CAN specification 2.0B
REC
CAN Core
TEC
? Bit timin g compliant with ISO-11898-1
? 16 Mailbox version
? 15 pro g rammable Mailboxes for transmit/receive
BCR
Transmit Buffer
Receive Buffer
Control
s ignal s
Statu s
s ignal s
+ 1 receive-only Mailbox
? Sleep mode for low power consumption and automatic
Microprocessor
Interface
recovery from sleep mode by detectin g CAN bus activity
MCR
IRR
Mailbox Control
? P ro g rammable receive filter mask (standard and
extended identifier) supported by all Mailboxes
16-bit
peripheral
bus
GSR
IMR
Mailbox 0 to 15
(RAM)
? P ro g rammable CAN data rate up to 1MBit/s
? Transmit messa g e queuin g with internal priority
sortin g mechanism
Mailbox 0 to 15
(regi s ter)
RCAN-ET Architecture
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