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参数资料
| 型号： | R1LV1616R |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | 16Mb superSRAM (1M wordx16bit) |
| 中文描述： | 16Mb的superSRAM（100万wordx16bit） |
| 文件页数： | 15/16页 |
| 文件大小： | 122K |
| 代理商： | R1LV1616R |
R1LV1616R Series
Rev.1.00
2004.04.13
page 15 of 16
Data Retention Characteristics
Note 1. Typical parameter of
Icc
DR
indicates the value for the center of distribution at Vcc=3.0V and not 100% tested.
2. BYTE# pin supported by TSOP type. BYTE#
≥
Vcc-0.2V or BYTE#
≤
0.2V
3. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer .If CS2
controls data retention mode,Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance
state. If CS1# controls data retention mode, CS2 must be CS2
≥
Vcc-0.2V or 0V
≤
CS2
≤
0.2V. The other input
levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state.
Data Retention timing Waveform (1) (LB#,UB# Controlled)
Data Retention timing Waveform (2) (CS1# Controlled)
Data Retention timing Waveform (3) (CS2 Controlled)
LB#
UB#
Vcc
t
CDR
t
R
2.4V
2.4V
2.70V
LB# =UB#
≥
Vcc-0.2V
CS2
Vcc
t
CDR
t
R
0.2V
0.2V
2.70V
0V
≤
CS2
≤
0.2V
Vcc
CS1#
t
CDR
t
R
2.4V
2.4V
2.70V
CS1#
≥
Vcc-0.2V
~+85oC
μA
40
-
-
ms
-
-
5
t
R
Operation recovery time
See retention waveform
ns
-
-
0
t
CDR
Chip deselect to data retention time
~+70oC
μA
25
-
-
~+40oC
μA
12
4
-
Vcc=3.0V,Vin
≥
0V
(1) 0V
≤
CS2
≤
0.2V or
(2) CS2
≥
Vcc-0.2V,
CS1#
≥
Vcc-0.2V or
(3) LB# =UB#
≥
Vcc-0.2V,
CS2
≥
Vcc-0.2V,
CS1#
≤
0.2V
Average value
Test conditions
*2,3
Unit
Typ.
*1
~+25oC
μA
6
2
-
Icc
DR
Data retention current
V in
≥
0V
(1) 0V
≤
CS2
≤
0.2V or
(2) CS2
≥
Vcc-0.2V,
CS1#
≥
Vcc-0.2V or
(3) LB# =UB#
≥
Vcc-0.2V,
CS2
≥
Vcc-0.2V,
CS1#
≤
0.2V
V
3.6
-
2.0
V
DR
Vcc for data retention
Max.
MIn.
Symbol
Parameter
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| R1LV1616R_07 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:16Mb Advanced LPSRAM (1M wordx16bit / 2M wordx8bit) |
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| R1LV1616RBG-5S | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:16Mb Advanced LPSRAM (1M wordx16bit / 2M wordx8bit) |
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