参数资料
型号: R1Q2A3636ABG-60R
厂商: Renesas Technology Corp.
英文描述: 36-Mbit QDR™II SRAM 2-word Burst
文件页数: 8/25页
文件大小: 394K
代理商: R1Q2A3636ABG-60R
R1Q2A3636/R1Q2A3618/R1Q2A3609
K Truth Table
Operation
K
/R
×
/W
L
D or Q
Data in
Input data
Output clock
Data out
Output data
Output clock
D =
×
or Q = High-Z
Previous state
D(A+0)
K(t)
D(A+1)
/K(t)
Write Cycle:
Load address, input write data on
consecutive K and /K rising edges
Q(A+0)
/C(t+1)
Q(A+1)
C(t+2)
Read Cycle:
Load address, output read data on
consecutive C and /C rising edges
L
×
NOP (No operation)
Standby (Clock stopped)
Notes: 1. H: high level, L: low level,
×
: don’t care,
: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges,
except if C and /C are high, then data outputs are delivered at K and /K rising edges.
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and
/C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits
most rapid restart by overcoming transmission line charging symmetrically.
H
×
H
×
Stopped
REJ03C0294-0003 Rev.0.03 Jul. 31, 2007
Page 8 of 23
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相关代理商/技术参数
参数描述
R1Q2A3636ABG60RB0 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst
R1Q2A3636ABG60RS0 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst
R1Q2A3636ABG60RT0 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst
R1Q2A3636B 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst
R1Q2A3636BBG-40I 制造商:Renesas Electronics Corporation 功能描述: