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参数资料
| 型号： | R1Q3A3618ABG-40R |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | 36-Mbit QDR™II SRAM 4-word Burst |
| 文件页数： | 7/26页 |
| 文件大小： | 407K |
| 代理商： | R1Q3A3618ABG-40R |
R1Q3A3636/R1Q3A3618/R1Q3A3609
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
Status
Power Up
Unstable
Clock Stage
Stop
Clock Stage
NOP & DLL
Locking Stage
Normal
Operation
V
DD
C, /C, K, /K
30ns min.
1024cycle min.
V
DDQ
V
REF
/DOFF
DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as
TKC var.
2. The lower end of the frequency at which the DLL can operate is 100MHz.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to V
SS
through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250
typical. The total external capacitance of ZQ ball must be less than 7.5
pF.
REJ03C0295-0003 Rev.0.03 Jul. 31, 2007
Page 7 of 24
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R1Q3A3618ABG40RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q3A3618ABG40RS0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q3A3618ABG40RT0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q3A3618ABG-50R | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR™II SRAM 4-word Burst |
| R1Q3A3618ABG50RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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