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参数资料
| 型号： | R1Q3A3618ABG-60R |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | 36-Mbit QDR™II SRAM 4-word Burst |
| 文件页数： | 11/26页 |
| 文件大小： | 407K |
| 代理商： | R1Q3A3618ABG-60R |
R1Q3A3636/R1Q3A3618/R1Q3A3609
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Unit
V
V
V
1
V
2, 3
V
2, 3
Parameter
Symbol
V
DD
V
DDQ
V
REF
V
IH (DC)
V
IL (DC)
Min
1.7
1.4
0.68
Typ
1.8
1.5
0.75
Max
1.9
V
DD
0.95
Notes
Power supply voltage --core
Power supply voltage --I/O
Input reference voltage --I/O
Input high voltage
Input low voltage
Notes: 1. Peak to peak AC component superimposed on V
REF
may not exceed 5% of V
REF
.
2. Overshoot: V
IH (AC)
≤
V
DDQ
+ 0.5 V for t
≤
t
KHKH
/2
Undershoot: V
IL (AC)
≥
0.5 V for t
≤
t
KHKH
/2
Power-up: V
IH
≤
V
DDQ
+ 0.3 V and V
DD
≤
1.7 V and V
DDQ
≤
1.4 V for t
≤
200 ms
During normal operation, V
DDQ
must not exceed V
DD
.
Control input signals may not have pulse widths less than t
KHKL
(min) or operate at cycle rates less than t
KHKH
(min).
During normal operation, V
IH(DC)
must not exceed V
DDQ
and V
IL(DC)
must not be lower than V
SS
.
3. These are DC test criteria. The AC V
IH
/ V
IL
levels are defined separately to measure timing parameters.
V
REF
+
0.1
0.3
V
DDQ
+
0.3
V
REF
0.1
DC Characteristics
(Ta = 0 to +70
°
C, V
DD
= 1.8V
±
0.1V)
50
60
Max
Max
550
500
600
550
650
600
30
Max
700
750
800
33
Max
650
700
750
40
Max
600
650
700
Parameter
Symbol
I
DD
I
DD
I
DD
Unit
mA
mA
mA
Notes
1, 2, 3
1, 2, 3
1, 2, 3
(×9)
(×18)
(×36)
Operating
supply current
(READ /
WRITE)
Standby supply
current (NOP)
(×9 /
×18 /
×36)
I
SB1
400
380
350
340
330
mA
2, 4, 5
Parameter
Symbol
I
LI
I
LO
V
OH
(Low)
V
OH
V
OL
(Low)
V
OL
Min
2
5
Max
2
5
V
DDQ
Unit
μA
μA
V
V
V
V
Test conditions
|I
OH
|
≤
0.1 mA
Note 6
I
OL
≤
0.1 mA
Note 7
Notes
10
11
8, 9
8, 9
8, 9
8, 9
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Notes: 1. All inputs (except ZQ, V
REF
) are held at either V
IH
or V
IL
.
2. I
OUT
= 0 mA. V
DD
= V
DD
max, t
KHKH
= t
KHKH
min.
3. Operating supply currents are measured at 100% bus utilization.
4. All address / data inputs are static at either V
IN
> V
IH
or V
IN
< V
IL
.
5. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
6. Outputs are impedance-controlled. |I
OH
| = (V
DDQ
/2)/(RQ/5) for values of 175
≤
RQ
≤
350
.
7. Outputs are impedance-controlled. I
OL
= (V
DDQ
/2)/(RQ/5) for values of 175
≤
RQ
≤
350
.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I standards.
10. 0
≤
V
IN
≤
V
DDQ
for all input balls (except V
REF
, ZQ, TCK, TMS, TDI ball).
11. 0
≤
V
OUT
≤
V
DDQ
(except TDO ball), output disabled.
V
DDQ
0.2
V
DDQ
/2
0.08
V
SS
V
DDQ
/2
0.08
V
DDQ
/2 +0.08
0.2
V
DDQ
/2 +0.08
REJ03C0295-0003 Rev.0.03 Jul. 31, 2007
Page 11 of 24
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相关代理商/技术参数 |
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|---|---|
| R1Q3A3618ABG60RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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| R1Q3A3618ABG60RT0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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| R1Q3A3618BBG-33RB0 | 制造商:Renesas Electronics Corporation 功能描述: |
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