参数资料
型号: R1RW0404D
厂商: Renesas Technology Corp.
英文描述: 4M HIGH SPEED SRAM (1-MWORD X 4-BIT)
中文描述: 4分高速SRAM(1 - MWORD × 4位)
文件页数: 7/13页
文件大小: 88K
代理商: R1RW0404D
R1RW0404D Series
Rev.1.00, Mar.12.2004, page 7 of 11
Write Cycle
R1RW0404D
-2
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
12
6
ns
Address valid to end of write
8
ns
Chip select to end of write
8
ns
9
Write pulse width
8
ns
8
Address setup time
0
ns
6
Write recovery time
0
ns
7
Data to write time overlap
6
ns
Data hold from write time
0
ns
Write disable to output in low-Z
3
ns
1
Output disable to output in high-Z
ns
1
Write enable to output in high-Z
Notes: 1. Transition is measured
±
200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6. t
AS
is measured from the latest address transition to the later of CS# or WE# going low.
7. t
WR
is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. t
WP
is measured from the beginning of write to the
end of write.
9. t
CW
is measured from the later of CS# going low to the end of write.
6
ns
1
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