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参数资料
| 型号： | R3116N441C-TR-FE |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封装： | HALOGEN AND LEAD FREE, SOT-23, 5 PIN |
| 文件页数： | 23/25页 |
| 文件大小： | 441K |
| 代理商： | R3116N441C-TR-FE |
R3116x
7
TIMING CHART
GND
Detect Delay Time (tPHL)
Output Delay Time (tD)
Supply
Voltage
(VDD)
Output
Voltage
(VOUT)
CD Pin
Voltage
(-VDET)
(+VDET)
Detector Threshold
Released Voltage
CD Pin Threshold Voltage
(VTCD)
Output Delay Time
Output Delay Time (tD) can be calculated with the next formula using the external capacitor:
tD(s)
= 4.5 × 106 × CD(F)
DEFINITION OF OUTPUT DELAY TIME
Output Delay Time (tD) is defined as follows:
1. In the case of Nch Open Drain Output:
Under the condition of the output pin (OUT) is pulled up through a resistor of 470k
Ω to 5V, the time interval
between the rising edge of VDD pulse from (-VDET)
0.1V to (-VDET)×1.1V pulse voltage is supplied, the
becoming of the output voltage to 2.5V.
2. In the case of CMOS Output:
The time interval between the rising edge of VDD pulse from (-VDET)
0.1V to (-VDET)×1.1V pulse voltage is
supplied, the becoming of the output voltage to ((-VDET)
×1.1V)/2.
Supply
Voltage
(VDD)
Output
Voltage
(VOUT)
VDET×1.1V
VDET0.1V
GND
5.0V
2.5V
GND
tD
tPHL
VDET0.1V
GND
tD
tPHL
VDET×1.1V
(
VDET×1.1V)/2
VDET×1.1V
Supply
Voltage
(VDD)
Output
Voltage
(VOUT)
Nch Open Drain Output
CMOS Output
(R3116xxx1A)
(R3116xxx1C)
When the supply voltage, which is higher than
released voltage, is forced to VDD pin, charge to
an external capacitor starts, then CD pin voltage
increases. Until the CD pin voltage reaches to CD
pin threshold voltage, output voltage maintains
"L". When the CD pin voltage becomes higher
than CD pin threshold voltage, output voltage is
reversed from "L" to "H". Where the time interval
between the rising edge of supply voltage and
output voltage reverse point means output delay
time.
When the output voltage reverses from "L" to
"H", the external capacitor starts to discharge.
Therefore, when lower voltage than the detector
threshold voltage is forced to VDD pin, the output
voltage reverses from "H" to "L" thus the detect
delay time is constant not being affected by the
external capacitor.
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