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参数资料
| 型号： | R5105N261C-TR-F |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6 |
| 封装： | ROHS COMPLIANT, SOT-23, 6 PIN |
| 文件页数： | 1/2页 |
| 文件大小： | 248K |
| 代理商： | R5105N261C-TR-F |
R5105N Series
Compact Watchdog Timer with VD
No.EK-159-091101
CMOS Microprocessor Supervisory
The R5105N Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single
chip. R5105N monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset
signal when a malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted high
accuracy with an external capacitor.
FEATURES
Supply Current (I
SS
) Typ. 11
μA (VDD=-VDET+0.5V,
Clock pulse input)
Operating Voltage Range (V
DD
) 0.9V to 6.0V
(VD Section)
Detector Threshold Range (-V
DET
) 1.5V to 5.5V (internally fixed)
Detector Threshold Accuracy ± 1%
Temp. coeff. of Detector Threshold Typ. ± 100ppm/°C
Output Delay Time (t
PLH
) Typ. 370ms (CD=0.1
μF)
Output Delay Time Accuracy ± 16% (-40°C <= Topt <= 105°C)
(WDT Section)
Watchdog Timeout Period (t
WD
) Typ. 310ms (CTW=0.1
μF)
Reset Hold Time of WDT (t
WR
) Typ. 34ms (CTW=0.1
μF)
Watchdog Timeout Period Accuracy ± 33% (-40°C <= Topt <= 105°C)
Package SOT-23-6
(The above shows specification at Topt=25°C. Design assurance value at -40°C <
= Topt <
= 105°C is also available. For details, please refer to the datasheet.)
BLOCK DIAGRAMS
TYPICAL APPLICATION
R5105Nxx1A
(Nch. open drain output)
VDD
GND
SCK
RESETB
CD
CTW
WATCHDOG
TIMER
CLOCK
DETECTOR
3
6
2
4
5
1
Vref2
Vref1
R5105Nxx1C
(CMOS output)
VDD
GND
SCK
RESETB
CD
CTW
3
6
2
4
5
1
WATCHDOG
TIMER
CLOCK
DETECTOR
Vref2
Vref1
CD
VDD
RESE T
I/O
R
CTW
GND
VDD
CD
RESETB
SCK
CTW
3
6
5
2
4
1
Microprocessor
R5105Nxx1A
Series
Power S upply
SELECTION GUIDE
Package
Quantity per Reel
Part No.
SOT-23-6
3,000 pcs
R5105N.xx.1.
-TR-F
.xx. : Specify the detector threshold within the range 1.5V (.15.) to 5.5V (.55.)
in 0.1V steps.
. : Select the output type from (.A.) Nch. open drain or (.C.) CMOS.
PACKAGE (Top View)
TIMING CHART
SOT-23-6
6
5
4
1
2
3
1
SCK
Watchdog timer clock input pin
2
CTW
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
3
VDD
Power supply pin
4
RESETB
Output pin for Reset "L" signal
5
GND
Ground pin
6
CD
Ext. Cap. pin for setting output
delay time of VD
APPLICATION
Monitoring of the power system of devices equipped with microprocessors
-VDET
+VDET
VRESETB
tWR
VCTW
VSCK
VDD
Vref2H
Vref2L
tPLH
VCD
tPHL
tPLH
tWDI
tWD
-VTCD
+VTCD
tPHL : Output delay time
tWDI : tWD/10 (SCK pulses input during this period are ignored.)
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