R5108G
7
OPERATION
M When the SENSE pin voltage becomes more than the released voltage (+VDET), after the released delay
time (or the power on reset time tpLH), the output of RESETB becomes “H” level.
N When the SCK pulse is input, the watchdog timer is cleared, and TW pin mode changes from discharge
mode to charge mode. When the TW pin voltage becomes higher than VREFH, the mode will change into
discharge, and next watchdog time count starts.
O Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of TW pin,
RESETB="L".
P When the SENSE pin becomes lower than the detector threshold voltage, RESETB outputs "L".
Q If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
R When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock.
Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to TW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD(s) = 3.1*10
6× C (F)
tWR(s)=tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the
next reset hold time RESETB pin outputs "L".
After starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse
is input during the time period "TWDI", the clock pulse is ignored.
TWDI[s]=TWD/10
Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation describes the
relation between the capacitance value and the released delay time (tpLH).
tpLH(s)=3.7
×10
6× C(F)
Note that the temperature dependence graph in the typical characteristics does not contain the temperature characteristics
of the external capacitor.
Minimum Operating Voltage (VINL)
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB pin being
0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100k
in the case of the Nch open-drain output type.
Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be dominant by the
voltage detector's operation. Therefore, if the SENSE pin voltage is set at more than the detector threshold level, RESETB
outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor (TYP. 110k
) internally.