参数资料
型号: R5F21154DDD
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, MICROCONTROLLER, PDIP20
封装: 0.300 INCH, 1.78 MM PITCH, PLASTIC, SDIP-20
文件页数: 4/36页
文件大小: 650K
代理商: R5F21154DDD
Rev.0.10
Sep 06, 2004
Page 12 of 34
REJ03B0102-0010Z
Under development
R8C/14, R8C/15 Group
2. Central Processing Unit (CPU)
Preliminary specification
Specifications in this manual are tentative and subject to change.
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1
and R3. The R0 register can be split into high-order bit (R0H) and low-order bit (R0L) to be used
separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be
combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
2.2
Address Registers (A0 and A1)
The A0 register is a 16-bit register for address register indirect addressing and address register relative
addressing. They also are used for transfer and arithmetic and logic operations. Same applies to A1 as
A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB, 20-bit register indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC, 20 bits wide indicates the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16-bit wide each. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debug only. Set to “0”.
2.8.3
Zero Flag (Z Flag)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4
Sign Flag (S Flag)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is
set to “1”.
2.8.6
Overflow Flag (O Flag)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
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