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| 型号： | R5F21236DFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 30/38页 |
| 文件大小： | 473K |
| 代理商： | R5F21236DFP |
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Section 2 CPU
Rev. 2.00 Aug. 28, 2007 Page 24 of 1106
REJ09B0230-0200
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly in memory.
Delayed Branching: Unconditional branch instructions means the delayed branch instructions.
With a delayed branch instruction, the branch is made after execution of the instruction
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made. The conditional branch instructions have two types of instructions:
conditional branch instructions and delayed branch instructions.
Table 2.3
Delayed Branch Instructions
CPU in this LSI
Description
Example of Other CPUs
BRA
TRGET
ADD
R1,R0
ADD is executed before branch to TRGET.
ADD.W R1,R0
BRA
TRGET
Multiply/Multiply-and-Accumulate Operations: A 16
× 16 → 32 multiply operation is
executed in one to two cycles, and a 16
× 16 + 64 → 64 multiply-and-accumulate operation in two
to three cycles. A 32
× 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-
accumulate operation are each executed in two to four cycles.
T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is
performed according to whether the result is True or False. Processing speed has been improved
by keeping the number of instructions that modify the T bit to a minimum.
Table 2.4
T Bit
CPU in this LSI
Description
Example of Other CPUs
CMP/GE
R1,R0
When R0
≥ R1, the T bit is set.
CMP.W R1,R0
BT
TRGET0
When R0
≥ R1, a branch is made to TRGET0. BGE
TRGET0
BF
TRGET1
When R0 < R1, a branch is made to TRGET1. BLT
TRGET1
ADD
#
1,R0
The T bit is not changed by ADD.
SUB.W #1,R0
CMP/EQ
#0,R0
When R0 = 0, the T bit is set.
BEQ
TRGET
BT
TRGET
A branch is made when R0 = 0.
Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword
immediate data is not placed in the instruction code. It is placed in a table in memory. The table in
memory is accessed with the MOV immediate data instruction using PC relative addressing mode
with displacement.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R5F21236DFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 32KB Flash 3.3V/5V 48-Pin LQFP Tray 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 32KB FLASH 3.3V/5V 48LQFP - Trays 制造商:Renesas Electronics 功能描述:MCU 16-Bit R8C CISC 32KB Flash 3.3V/5V 48-Pin LQFP Tray Tray 制造商:Renesas Electronics Corporation 功能描述:IC R8C/23 MCU FLASH 48LQFP 制造商:Renesas 功能描述:MCU 16-Bit R8C CISC 32KB Flash 3.3V/5V 48-Pin LQFP Tray |
| R5F21236DFP#V0 | 功能描述:IC R8C/23 MCU FLASH 48LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/23 标准包装:250 系列:80C 核心处理器:8051 芯体尺寸:8-位 速度:16MHz 连通性:EBI/EMI，I²C，UART/USART 外围设备:POR，PWM，WDT 输入/输出数:40 程序存储器容量:- 程序存储器类型:ROMless EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-LCC（J 形引线） 包装:带卷 (TR) |
| R5F21236DFPU0 | 制造商:Renesas Electronics Corporation 功能描述:16bit MCU,R8C,32K ROM,2K RAM,LFQFP64 |
| R5F21236JFP | 功能描述:MCU 3/5V 32K+2K 48-LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/23 标准包装:250 系列:80C 核心处理器:8051 芯体尺寸:8-位 速度:16MHz 连通性:EBI/EMI，I²C，UART/USART 外围设备:POR，PWM，WDT 输入/输出数:40 程序存储器容量:- 程序存储器类型:ROMless EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-LCC（J 形引线） 包装:带卷 (TR) |
| R5F21236JFP#U0 | 制造商:Renesas Electronics Corporation 功能描述: |
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