
R8C/3GM Group
26. Hardware LIN
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
Figure 26.7
Header Field Reception Flowchart Example (2)
Timer RA
Set pulse width measurement to start
TSTART bit in TRACR register
← 1
Timer RA
Read the count status flag
TCSTF flag in TRACR register
Hardware LIN Set Synch Break detection to start
LSTART bit in LINCR register
← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in LINCR register
A
TCSTF = 1?
YES
RXDSF = 1?
YES
NO
Wait until timer RA starts counting.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST
register
← 1
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
SBDCT = 1?
YES
NO
B
After writing 1 to the LSTART bit,
do not apply a “L” level to the RXD0 pin
until 1 is read from the RXDSF flag.
Otherwise, the signal applied during
this time will be input directly to UART0.
One or two cycles of the CPU clock and
zero or one cycle of the timer RA count
source are required after the LSTART
bit is set to 1 before the RXDSF flag is
set to 1. After this, input to timer RA
and UART0 is enabled.
A Synch Break for the hardware LIN is
detected.
A timer RA interrupt can be used.
Wait until the RXD0 input to UART0 for
the hardware LIN is masked.
When a Synch Break is detected,
timer RA is reloaded with the initially
set count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the initially
set count value. Wait until the next “L”
level is input.
One or two cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
If the SBE bit in the LINCR register is
set to 0 (unmasked after Synch Break
detected), timer RA can be used in
timer mode after the SBDCT flag in
the LINST register is set to 1 and the
RXDSF flag is set to 0.
Zero or one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set
to 1.