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| 型号： | R5F2L36CANFA |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 53/87页 |
| 文件大小： | 1311K |
| 代理商： | R5F2L36CANFA |
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5. Electrical Characteristics
REJ03B0243-0030 Rev.0.30
Jan 21, 2009
Page 57 of 76
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
Notes:
1.
The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
2.
Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3.
Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Notes:
1.
This condition (external power VCC rise gradient) does not apply if VCC
≥ 1.0 V.
2.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Figure 5.3
Power-on Reset Circuit Characteristics
Table 5.11
Voltage Detection 2 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr =
20 to 85°C (N version) / 40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
Vdet2
Voltage detection level Vdet2_0 (1)
At the falling of VCC
TBD
4.00
TBD
V
Voltage detection level Vdet2_EXT (1)
At the falling of LVCMP2
TBD
1.34
TBD
V
Hysteresis width at the rising of Vcc in voltage detection
2 circuit
0.10
V
Voltage detection 2 circuit response time (2)
At the falling of Vcc from
5 V to (Vdet2_0
0.1) V
20
150
s
Voltage detection circuit self power consumption
VCA27 = 1, VCC = 5.0 V
1.7
A
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
100
s
Table 5.12
Power-on Reset Circuit Characteristics (2)
(Topr =
20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
trth
0
50000
mV/msec
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual (REJ09B0441) for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Vdet0 (1)
0.5 V
Internal
reset signal
tw(por) (2)
Voltage detection 0
circuit response time
Vdet0 (1)
1
fOCO-S
× 32
1
fOCO-S
× 32
External
Power VCC
trth
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