参数资料
型号: R5F2L388CNFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封装: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件页数: 17/74页
文件大小: 959K
代理商: R5F2L388CNFP
25
2588F–AVR–06/2013
ATtiny261/461/861
6.1.3
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
6.1.4
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
6.1.5
Fast Peripheral Clock – clk
PCK
Selected peripherals can be clocked at a frequency higher than the CPU core. The fast periph-
eral clock is generated by an on-chip PLL circuit.
6.1.6
PLL System Clock – clk
ADC
The PLL can also be used to generate a system clock. The clock signal can be prescaled to
avoid overclocking the CPU.
6.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note:
1. For all fuses “1” means unprogrammed and “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before com-
Table 6-1.
Device Clocking Options Select(1) vs. PB4 and PB5 Functionality
Device Clocking Option
CKSEL3:0
PB4
PB5
0000
XTAL1
I/O
0001
I/O
0010
I/O
0011
I/O
01xx
XTAL1
XTAL2
0.4...0.9 MHz (see page 30)
1000
1001
XTAL1
XTAL2
0.9...3.0 MHz (see page 30)
1010
1011
XTAL1
XTAL2
3...8 MHz (see page 30)
1100
1101
XTAL1
XTAL2
8...20 MHz (see page 30)
1110
1111
XTAL1
XTAL2
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