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参数资料
型号： R5F364AENFA
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封装： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件页数： 4/92页
文件大小： 736K
代理商： R5F364AENFA
R01DS0032EJ0200 Rev.2.00
Page 12 of 88
Feb 07, 2011
M16C/64A Group
1. Overview
Notes:
1.
Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics.
2.
TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
Table 1.7
Pin Functions for the 100-Pin Package (2/3)
Signal Name
Pin Name
I/O
Power
Supply
Description
Main clock input
XIN
I
VCC1 I/O for the main clock oscillator. Connect a ceramic resonator
or crystal between pins XIN and XOUT. (1) Input an external
clock to XIN pin and leave XOUT pin open.
Main clock output
XOUT
O
VCC1
Sub clock input
XCIN
I
VCC1 I/O for a sub clock oscillator. Connect a crystal between XCIN
pin and XCOUT pin. (1) Input an external clock to XCIN pin and
leave XCOUT pin open.
Sub clock output
XCOUT
O
VCC1
BCLK output
BCLK
O
VCC2 Outputs the BCLK signal.
Clock output
CLKOUT
O
VCC2 Outputs a clock with the same frequency as fC, f1, f8, or f32.
INT interrupt input
INT0 to INT2
I
VCC1
Input for the
INT interrupt.
INT3 to INT7
I
VCC2
NMI interrupt input
NMI
I
VCC1 Input for the
NMI interrupt.
Key input interrupt
input
KI0 to KI3
I
VCC1 Input for the key input interrupt.
Timer A
TA0OUT to
TA4OUT
I/O
VCC1
I/O for timers A0 to A4 (TA0OUT is N-channel open drain
output).
TA0IN to TA4IN
I
VCC1 Input for timers A0 to A4.
ZP
I
VCC1 Input for Z-phase.
Timer B
TB0IN to TB5IN
I
VCC1 Input for timers B0 to B5.
Three-phase motor
control timer
U,
U, V, V, W, W O
VCC1 Output for the three-phase motor control timer.
SD
I
VCC1 Forced cutoff input.
IDU, IDV, IDW
I
VCC2 Input for the position data.
Real-time clock output
RTCOUT
O
VCC1 Output for the real-time clock.
PWM output
PWM0, PWM1
O
VCC1,
VCC2
PWM output.
Remote control signal
receiver input
PMC0, PMC1
I
VCC1 Input for the remote control signal receiver.
Serial interface
UART0 to UART2,
UART5 to UART7
CTS0 to CTS2,
CTS5
I
VCC1
Input pins to control data transmission.
CTS6, CTS7
I
VCC2
RTS0 to RTS2,
RTS5
O
VCC1
Output pins to control data reception.
RTS6, RTS7
O
VCC2
CLK0 to CLK2,
CLK5
I/O
VCC1
Transmit/receive clock I/O.
CLK6, CLK7
I/O
VCC2
RXD0 to RXD2,
RXD5
I
VCC1
Serial data input.
RXD6, RXD7
I
VCC2
TXD0 to TXD2,
TXD5
O
VCC1
Serial data output. (2)
TXD6, TXD7
O
VCC2
CLKS1
O
VCC1 Output for the transmit/receive clock multiple-pin output function.
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