参数资料
型号: R5F562N7BDBG#U0
厂商: Renesas Electronics America
文件页数: 3/148页
文件大小: 0K
描述: MCU 32BIT FLASH 384KROM 176LFBGA
产品培训模块: RX Compare Match Timer
RX DMAC
标准包装: 1
系列: RX600
核心处理器: RX
芯体尺寸: 32-位
速度: 100MHz
连通性: CAN,EBI/EMI,I²C,SCI,SPI,USB
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 126
程序存储器容量: 384KB(384K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x10/12b,D/A 2x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 176-LFBGA
包装: 托盘
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 98
2004 Microchip Technology Inc.
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority Registers (IPR1, IPR2 and IPR3). The
operation of the priority bits requires that the Interrupt
Priority Enable (IPEN) bit be set.
REGISTER 9-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1
= High priority
0
= Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
RC1IP: USART1 Receive Interrupt Priority bit
1
= High priority
0
= Low priority
bit 4
TX1IP: USART1 Transmit Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1
= High priority
0
= Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1
= High priority
0
= Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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