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参数资料
| 型号： | R80188 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 8 MHz, MICROPROCESSOR, CQCC68 |
| 封装： | CERAMIC, LCC-68 |
| 文件页数： | 32/33页 |
| 文件大小： | 372K |
| 代理商： | R80188 |
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8018680188
Table 1 Pin Descriptions
(Continued)
Symbol
Pin
Type
Name and Function
No
HOLD
50
I
HOLD indicates that another bus master is requesting the local bus The
HOLD input is active HIGH HOLD may be asynchronous with respect to the
HLDA
51
O
processor clock The processor will issue a HLDA (HIGH) in response to a
HOLD request at the end of T4 or Ti Simultaneous with the issuance of
HLDA the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will lower HLDA When the processor
needs to run another bus cycle it will again drive the local bus and control
lines
UCS
34
O
Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K – 256K block) of memory
This line is not floated during bus HOLD The address range activating UCS is
software programmable
LCS
33
O
Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K – 256K) of memory This line is not
floated during bus HOLD The address range activating LCS is software
programmable
MCS0
38
O
Mid-Range Memory Chip Select signals are active LOW when a memory
reference is made to the defined mid-range portion of memory (8K – 512K)
MCS1
37
O
These lines are not floated during bus HOLD The address ranges activating
MCS2
36
O
MCS0 – 3 are software programmable
MCS3
35
O
PCS0
25
O
Peripheral Chip Select signals 0 – 4 are active LOW when a reference is made
to the defined peripheral area (64 Kbyte IO space) These lines are not
PCS1
27
O
floated during bus HOLD The address ranges activating PCS0 – 4 are
PCS2
28
O
software programmable
PCS3
29
O
PCS4
30
O
PCS5 A1
31
O
Peripheral Chip Select 5 or Latched A1 may be programmed to provide a
sixth peripheral chip select or to provide an internally latched A1 signal The
address range activating PCS5 is software-programmable PCS5 A1 does
not float during bus HOLD When programmed to provide latched A1 this pin
will retain the previously latched value during HOLD
PCS6 A2
32
O
Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select or to provide an internally latched A2 signal
The address range activating PCS6 is software programmable PCS6 A2
does not float during bus HOLD When programmed to provide latched A2
this pin will retain the previously latched value during HOLD
DTR
40
O
Data TransmitReceive controls the direction of data flow through an
external data bus transceiver When LOW data is transferred to the
processsor When HIGH the processor places write data on the data bus
DEN
39
O
Data Enable is provided as a data bus transceiver output enable DEN is
active LOW during each memory and IO access DEN is HIGH whenever
DTR changes state During RESET DEN is driven HIGH for one clock then
floated DEN also floats during HOLD
NOTE
Pin names in parentheses apply to the 80188
8
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相关代理商/技术参数 |
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|---|---|
| R80188-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| R80188-10B | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:High Integration 8-Bit Microprocessor |
| R80188B | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:High Integration 8-Bit Microprocessor |
| R-801BXZ-4 | 制造商:OKAYA 制造商全称:OKAYA 功能描述:SURGE PROTECTOR |
| R-801BXZ-5 | 制造商:OKAYA 制造商全称:OKAYA 功能描述:SURGE PROTECTOR |
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