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6289D–ATARM–3-Oct-11
AT91SAM9R64/RL64
37.3.4
Programming a Channel
F our re gisters, the DMAC_DSCRx, the DM AC_CTRL Ax, th e DMAC_ CTRLBx an d
DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take
place, and which type of multi-buffer transfer is used. The different transfer types are shown in
The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx,
DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when
multi-buffer DMAC transfers are enabled.
37.3.4.1
Programming Examples
37.3.4.2
Single-buffer Transfer (Row 1)
1.
Read the Channel Handler Status Register DMAC_CHSR.ENABLE Field to choose a
free (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMAC transfer by read-
ing the interrupt status register, DMAC_EBCISR.
3.
Program the following channel registers:
a.
Write the starting source address in the DMAC_SADDRx register for channel x.
b.
Write the starting destination address in the DMAC_DADDRx register for channel
x.
c.
Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1
both DST_DSCR and SRC_DSCR fields set to one and AUTO field set to 0.
d.
Write the control information for the DMAC transfer in the DMAC_CTRLAx and
DMAC_CTRLBx registers for channel x. For example, in the register, you can pro-
gram the following:
– Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB Master interface layer in the SIF field where source resides.
– Destination AHB Master Interface layer in the DIF field where destination resides.
– Incrementing/decrementing or fixed address for source in SRC_INC field.
– Incrementing/decrementing or fixed address for destination in DST_INC field.
e.
Write the channel configuration information into the DMAC_CFGx register for chan-
nel x.
f.
If source picture-in-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is
enabled), program the DMAC_SPIPx register for channel x.
g.
If destination picture-in-picture mode is enabled (DMAC_CTRLBx.DST_PIP is
enabled), program the DMAC_DPIPx register for channel x.
4.
After the DMAC selected channel has been programmed, enable the channel by writing
a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n is the channel number. Make sure
that bit 0 of DMAC_EN.ENABLE register is enabled.
5.
Once the transfer completes, hardware sets the interrupts and disables the channel. At
this time you can either respond to the buffer Complete or Transfer Complete interrupts,
or poll for the Channel Handler Status Register (DMAC_CHSR.ENABLE[n]) bit until it is
cleared by hardware, to detect when the transfer is complete.