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参数资料
| 型号： | RC2211N |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FSK Demodulator/Tone Decoder |
| 中文描述： | FSK解调器/音频解码器 |
| 文件页数： | 7/16页 |
| 文件大小： | 135K |
| 代理商： | RC2211N |
RC2211
PRODUCT SPECIFICATION
7
FSK Decoding with Carrier Detector
The lock detector section of the RC2211 can be used as a
carrier detector option for FSK decoding. The recommended
circuit connection for this application is shown in Figure 3.
The open-collector lock detector output, pin 6, is shorted to
the data output (pin 7). Thus, the data output will be disabled
at òlowó state, until there is a carrier within the detection
band of the PLL, and the pin 6 output goes òhighó to enable
the data output.
Figure 3. External Connections for
FSK Demodulation with Carrier Detector Capability
The minimum value of the lock detector Tlter capacitance
C
D
is inversely proportional to the capture range,
±D
f
C
.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C
1
. For most applications,
D
F
C
<
D
F/2. For R
D
= 470 k
W
, the approximate minimum
value of C
D
can be determined by:
C
D
(
m
F)
3
16/capture range in Hz
With values of C
D
that are too small, chatter can be observed
on the lock detector output as an incoming signal frequency
approaches the capture bandwidth. Excessively large values
of C
D
will slow the response time of the lock detector
output.
Tone Detection
Figure 4 shows the generalized circuit connection for tone
detection. The logic outputs, Q and Q at pins 5 and 6 are
normally at òhighó and òlowó logic states, respectively.
When a tone is present within the detection band of the PLL,
the logic state at these outputs becomes reversed to the
duration of the input tone. Each logic output can sink 5 mA
of load current.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RC2211
65-2211-06
C0
VCO
Fine Tune
R0
R
X
5K
R1
C1
0.1
μ
F
R
F
100K
510K
C
F
Data
Output
5.1K
+V
S
C
O
470K
0.1
μ
F
0.1
μ
F
+V
S
FSK
Inputs
Note:
Data output is "low" when no carrier is present.
Figure 4. Circuit Connection for Tone Detection
Both logic outputs at pins 5 and 6 are open-collector type
stages, and require external pull-up resistors R
L1
and R
L2
as
shown in Figure 4.
With reference to Figures 1 and 4, the function of the
external circuit components can be explained as follows:
R
0
and C
0
set VCO center frequency, R
1
sets the detection
bandwidth, C
1
sets the lowpass-loop Tlter time constant and
the loop dampening factor, and R
L1
and R
L2
are the respec-
tive pull-up resistors for the Q and Q logic outputs.
Design Instructions
The circuit of Figure 4 can be optimized for any tone-detec-
tion application by the choice of Tve key circuit components:
R
0
, R
1
, C
0
, C
1
and C
D
. For a given input tone frequency, F
S
,
these parameters are calculated as follows:
1.
Choose R
0
to be in the range of 15 k
W
to 100 k
W
.
This choice is arbitrary.
2.
Calculate C
0
to set center frequency, f
0
equal to
F
S
: C
0
= 1/R
0
F
S
.
3.
Calculate R
1
to set bandwidth
±D
F (see Design Equa-
tion No. 5): R
1
= R
0
(F
0
/
D
F). Note: The total detection
bandwidth covers the frequency range of F
0
±
D
F.
4.
Calculate value of C
1
for a given loop damping factor:
C
1
=C
0
/16
z
2
Normally
z
= 1/2 is optimum for most tone detector
applications, giving C
1
= 0.25 C0.
Increasing C
1
improves the out-of-band signal rejection,
but increases the PLL capture time.
5.
Calculate value of Tlter capacitor C
D
. To avoid chatter
at the logic output, with R
D
= 470
W
, C
D
must be:
C
D
(
m
F)
3
(16/capture range in Hz)
Increasing C
D
slows the logic output response time.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RC2211
65-2211-07
C0
VCO
Fine Tune
R0
R
X
5K
R1
C1
0.1
μ
F
Logic
Output
+V
S
C
O
470K
0.1
μ
F
0.1
μ
F
+V
S
FSK
Inputs
Q
R
L1
R
L2
+V
S
Q
Logic
Outputs
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