
PRODUCT SPECIFICATION
RC5057
REV. 1.2.0 2/10/00
17
PCB Layout Guidelines
Placement of the MOSFETs relative to the RC5057 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the RC5057 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise radiates
throughout the board, and, because it is switching at such
a high voltage and frequency, it is very difficult to suppress.
In general, all of the noisy switching lines should be kept
away from the quiet analog section of the RC5057. That
is, traces that connect to pins 7, 9, 10, and 8 (LODRV,
HIDRV, SW and VCCP) should be kept far away from the
traces that connect to pins 3 through 5, and pin 11.
Place the 0.1F decoupling capacitors as close to the
RC5057 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
Each VCC and GND pin should have its own via to the
appropriate plane. This helps provide isolation between pins.
Place the MOSFETs, inductor, and Schottky as close
together as possible for the same reasons as in the first
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1F decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.
Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.
Additional Information
For additional information contact Fairchild Semiconductor at
http://www.fairchildsemi.com/cf/tsg.htm or contact an autho-
rized representative in your area.
Appendix
Worst-Case Formulae for the Calculation of
Cout, R5, and Cin (Circuit of Figure 1 Only)
The following formulae design the RC5057 for worst-case
operation, including initial tolerance and temperature depen-
dence of all of the IC parameters (initial setpoint, reference
tolerance and tempco, active droop tolerance, current sensor
gain), the initial tolerance and temperature dependence of
the MOSFET, and the ESR of the capacitors. The following
information must be provided:
VT+, the value of the positive transient voltage limit;
|VT-|, the absolute value of the negative transient voltage limit;
IO, the maximum output current;
Vnom, the nominal output voltage;
Vin, the input voltage (typically 5V);
ESR, the ESR of the output caps, per cap (44m
for the
Sanyo parts shown in this datasheet);
RD, the on-resistance of the MOSFET (10m for the
FDB7030);
RD, the tolerance of the current sensor (usually about 67%
for MOSFET sensing, including temperature).
Irms, the rms current rating of the input caps (2A for the
Sanyo parts shown in this datasheet).
The value of R5 must be
≤ 8.3K. If a greater values is
calculated, RD must be reduced.
Number of capacitors needed for Cout = the greater of:
2
Irms
Vin
Vnom
Vin
Vnom
*
IO
Cin
–
=
50 * 10
-6
IO* RD * (1 + RD) * 1.10
R5 =
VT-
ESR * IO
X=
18 * R5 * 1.1
14400 * IO * RD
Y
or
VT+ –0.004 * Vnom +
=