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参数资料
| 型号： | RC7105 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | RC71 SERIES, LOW SKEW CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 3/10页 |
| 文件大小： | 83K |
| 代理商： | RC7105 |
RC7105
PRODUCT SPECIFICATION
2
Advanced
Infor
mation
Pin Assignments
Pin Descriptions
Pin Name
Pin Number
Type
Pin Function Description
SDRAM0:12
2, 3, 6, 7, 10, 11,
18, 19, 22, 23,
26, 27, 12
OUT
SDRAM Outputs: Provides buffered copy of BUF_IN. The
propagation delay from a rising input edge to a rising output
edge is 1 to 5ns. All outputs are skew controlled to within
±250ps of each other.
BUF_IN
9
IN
Clock Input: This clock input has an input threshold voltage of
1.5V (typ).
SDA
14
IN/OUT
I2C Data input: Data should be presented to this input as
described in the I2C section of this data sheet.
SCL
15
IN
I2C clock input: The I2C clock should be presented to this input
as described in the I2C section of this data sheet.
VDD
1, 5, 13, 20, 24,
28
POWER
Power Connection: Power supply for core logic and output
buffers. Connected to 3.3V supply.
GND
4, 8, 16, 17, 21,
25
GROUND
Ground Connection: Connect all ground pins to the common
system ground plane.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
SCL
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDA
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