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参数资料
| 型号： | RD-14595D1-892L |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封装： | DDIP-36 |
| 文件页数： | 7/14页 |
| 文件大小： | 416K |
| 代理商： | RD-14595D1-892L |
2
SD-14595/96/97 SPECIFICATIONS
Specifications apply over temperature range, power supply range, ref-
erence frequency, and amplitude range; 15% signal amplitude varia-
tion, up to 10% harmonic distortion in the reference, and up to 45° of
signal to reference phase shift.
PARAMETER
UNIT
VALUE
RESOLUTION
Bits
14 or 16
REPEATABILTY
LSB
1 Max
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Range
Voltage Range
Input Impedance:
n Single Ended
n Differential
Common Mode Range
Hz
Vrms
Ohm
V
ACCURACY
Min
5.2, 2.6, or 1.3
DIGITAL INPUT/OUTPUT
Logic Type
Inputs:
Inhibit (INH)
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance)
Input Impedance Imbalance
n Synchro
Zin Line-to-Line
Zin Each Line-to-Gnd
Common Mode Range
Maximum Transient Peak
Voltage
n Resolver
Zin Single Ended
Zin Differential
Zin Each Line-to Gnd
Common Mode Range
Maximum Transient Peak
Voltage
n Direct (1.0 V L-L)
Input Signal Type
Sin/Cos Voltage Range
Max Voltage w/o Damage
Input Impedance
REFERENCE SYNTHESIZER
± Sig/Ref Phase Shift
0.2 max
11.8 V L-L 90 V L-L
17.5k
130k
11.5k
85k
30
180
150
11.8 V L-L
23k
46k
23k
60 max
150
Sin and Cos resolver sig-
nals referenced to converter
internal DC reference V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M // 10 pf voltage
follower
60 typ, 45 guaranteed
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 A max
Logic 0 inhibits Data stable
within 0.5 s (pull up)
47-1000 (60 Hz Unit)
360-1000 (400 Hz Unit)
4-130 (for 11.8 Vor 90 V sig-
nal input)
3-100 (for 1 V direct signal input)
250k min
500k min
250 peak max
%
V
Ohm
Vpeak
V
Ohm
V
Vrms
Ohm
Deg
PARAMETER
UNIT
VALUE
DIGITAL INPUT/OUTPUT
(cont)
Resolution Control (14B)
(for Programmable Units Only)
Enable Bits 1 to 8 (HBE)
Enable Bits 9 to 16 (LBE)
(9 to 14 for 14-bit mode)
Outputs:
Parallel Data
Converter Busy (CB)
BIT
Drive Capability
Bits
Logic 1 for 14 bits
Logic 0 for 16 Bits
Pull-up current source to
+5 V//5 pF max CMOS
transient protected
Logic 0 enables
Data Valid within 150 ns
Logic 1 = High Z
Data High Z within 100 ns
Pull-down current source
to GND//5 pF max CMOS
transient protected
14 or 16 parallel lines;
natural binary angles, posi-
tive logic (see TABLE 3)
0.8 to 3.0 s positive pulse;
leading edge initiates
counter update.
Logic 1 for fault conditions.
50 pF + rated logic drive
Logic 0; 1 TTL load,
1.6 mA at 0.4 V max
Logic 1; 10 TTL loads,
0.4 mA at 2.8 V min High
Z;10 A//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply
minus 100 mV min
driving CMOS
DYNAMIC CHARACTERISTICS
See TABLE 6
PHYSICAL CHARACTERISTICS
in
(mm)
oz(g)
.9 x 0.78 x 0.21
(48 x 20 x 5.3 )
36-Pin Double Dip
0.7 max (20)
TEMPERATURE
RANGES
Operating (-1XX or -4XX)
(-3XX or -8XX)
Storage
°C
-55 to +125
0 to 70
-65 to +150
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Tolerance
Max Voltage w/o Damage
Current
V
%
V
mA
+5
±10
+7
25 max+digital output load
TABLE 1. SD-14595/96/97 SPECIFICATIONS (CONT)
ANALOG OUTPUT
Analog Return (V)
Velocity (VEL) (See note 3.)
AC error (e)
n 14-Bit Mode
n 16-Bit Mode
Load
mVrms
mA
+4.3 V nom
See TABLE 4.
3.5 per LSB of error
1.75 per LSB of error
1
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