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参数资料
| 型号： | RD-19230FX-202T |
| 元件分类： | ADC |
| 英文描述： | Resolver-to-Digital Converter |
| 中文描述： | 分解器数字转换器 |
| 文件页数： | 14/20页 |
| 文件大小： | 152K |
| 代理商： | RD-19230FX-202T |
14
Data Device Corporation
www.ddc-web.com
RD-19230
SYNTHESIZED REFERENCE
The synthesized reference section of the RD-19230 eliminates
errors due to phase shift between the reference and signal
inputs. Quadrature voltages in a resolver or synchro are by def-
inition the resulting 90
°
fundamental signal in the nulled out error
voltage (e) in the converter. Due to the inductive nature of syn-
chros and resolvers, their output signals lead the reference input
signal (RH and RL). When an uncompensated reference signal
is used to demodulate the control transformer
’
s output, quadra-
ture voltages are not completely eliminated. As shown in
block diagram, FIGURE 1, on page 1, the converter synthesizes
its own internal reference signal based on the SIN and COS sig-
nal inputs.Therefore, the phase of the synthesized (internal) ref-
erence is determined by the signal input, resulting in reduced
quadrature errors.
BUILT-IN-TEST (BIT)
The BIT output is active low, and will be asserted during the
following three error conditions:
Loss of Signal (LOS) - Sin and Cos inputs both less than 500mV.
Loss of Reference (LOR) - Reference Input less than 500 mV.
Excessive Error - This error is detected by monitoring the
demodulator output, which is proportional to the difference
between the analog input and digital output. When it exceeds
approximately 100 LSBs (in the selected resolution), BIT will be
asserted. This condition can occur any time the analog input
changes at a rate in excess of the maximum tracking rate.
During power up, the converter may see a large difference
between the sin/cos inputs and the digital output angle held in its
counter. BIT will be asserted until the converter settles within
~ 100 LSB
’
s of the final result.
FIGURE 22. INCREMENTAL ENCODER EMULATION
2t
B(X- or LSB & LSB+1)
A (LSB+1)
ZIP (NRP)
359.95
0
T
t
DATA
VALID
50 nsec
D0/D1
A QUAD B
FIGURE 23.TIMING FOR INCREMENTAL ENCODER
EMULATION RESOLUTION CONTROL
RD-19230
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BIT 16 LSB
B
1
0
1
2
1
4
1
6
A
FIGURE 21. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
相关PDF资料 |
PDF描述 |
|---|---|
| RD-19230FX-203 | Resolver-to-Digital Converter |
| RD-19230FX-203T | Resolver-to-Digital Converter |
| RD-19230FX-302 | Resolver-to-Digital Converter |
| RD30HVF1 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | SOT-391VAR |
| RD6610ANP-011 | Analog Shift Register |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RD-19230FX-203 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-203T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:RESOLVER-TO-DIGITAL CONVERTER |
| RD-19230FX-302 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-302T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-303 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
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