参数资料
型号: RD-19230FX-203T
元件分类: ADC
英文描述: Resolver-to-Digital Converter
中文描述: 分解器数字转换器
文件页数: 11/20页
文件大小: 152K
代理商: RD-19230FX-203T
11
Data Device Corporation
www.ddc-web.com
RD-19230
2
1
-VCO
VEL
+5 V
-5 V
100 k
(OFFSET)
V
V
V
RD-19230
FIGURE 15.VELOCITY TRIMMING
UP/DN
The UP/DN input selects the gain of the amplifier driving the de-
selected set of bandwidth components. UP/DN has three input
states. See TABLE 6 to relate input to gain.
BENEFIT OF SWITCHING RESOLUTION ON THE FLY
Switching resolution on the fly can be used in applications that
require high resolution for accurate position control, and tracking
rates or settling times that are faster than the high resolution
mode will allow.
The RD-19230 can track four times faster for each step down in
resolution (i.e., a step from 16 bits to 14 bits). The velocity out-
put will be scaled down by a factor of four with each step down
in resolution. For example, if the velocity output is scaled such
that 4 Volts = 10 RPS in 16 bit resolution, then the same con-
verter will output 1 Volt for 10 RPS in 14 bit resolution. To avoid
glitches in the velocity output, the second set of bandwidth com-
ponents can be pre-charged to the expected voltage, and
switched in using the SHIFT input at the same time the resolu-
tion is changed. This will allow for a smooth velocity transition,
resulting in reduced errors and minimal settling time after the
change.
FIGURE 17, on page 12, shows the way the converter behaves
during a change in resolution while tracking at a constant veloc-
ity. The first illustration shows the benefits of switching in pre-
charged components while changing resolution. The second
illustration shows the result without the benefits of switching on
the fly.
The signals that have been recorded are:
1) VEL: velocity output pin on the RD-19230
2) ERROR:this is the analog representation of the error between
the input and the output of the RD-19230
3) D0: an input resolution control line to the RD-19230
4) BIT: built-in-test output pin of the RD-19230
DC INPUTS
As noted in TABLE 1, on page 2, the RD-19230 will accept DC
inputs. It is necessary to set the REF input to DC by tying RH to
+5 V and RL to GND or -5 \/.
VELOCITY TRIMMING
RD-19230 specifications for velocity scaling, reversal error, and
offset are listed in TABLE 1.Velocity scaling and offset are exter-
nally trimmable for applications requiring tighter specifications
than those available from the standard unit. FIGURE 15 shows
the setup for trimming these parameters with external pots. It
should also be noted that when the resolution is changed, VEL
Scaling is also changed.
OPTIONAL BANDWIDTH COMPONENTS
The RD-19230 provides the option of using a second set of
bandwidth components. The second set of components can be
used for switch-on-the-fly or dual-bandwidth applications. The
SHIFT and UP/DN inputs are used when switching bandwidth
components, and their operation is described below. Refer to the
block diagram, FIGURE 1, on page 1.
SHIFT
The SHIFT pin is an input that chooses between the VEL1 and
VEL2 bandwidth components. This pin has an internal pull-up to
+5V. When the SHIFT pin is left open, or a logic 1 is applied, the
VEL1 components are selected. When a Logic 0 is applied, the
VEL2 components are selected. The deselected set of band-
width components are driven by an amplifier, with programmable
gain, that follows the velocity amplifier. This amplifier can be
used to pre-charge the deselected set of components to the volt-
age level that is expected after a change in resolution. (See
description on BENEFIT OF SWITCHING RESOLUTION ON
THE FLY.)
TABLE 6. PRECHARGE AMPLIFIER
GAIN PROGRAMMING
UP/DN
Logic 1
4
Logic 0
1/4
-5 V
1
GAIN
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