参数资料
型号: RD151TS501USE
厂商: Renesas Technology Corp.
英文描述: PLL clock generator series
中文描述: PLL时钟发生器系列
文件页数: 5/7页
文件大小: 104K
代理商: RD151TS501USE
RD151TS501US
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 5 of 6
Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 3.
V
DD
decoupling is important to reduce Jitter performance.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
8
1
7
IN
6
SEL
PDWN
5
2
3
4
C2
C1
GND GND
VDD
DIV2
OUT
R1
GND
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1
μ
F recommended)
C2 = Low frequency supply decoupling capacitor.
(22
μ
F recommended)
R1 = Match value to line impedance.
(Please use R1 if nessesarry)
Figure 3 Recommended circuit configuration
Remark for use
Please do not use the pull-up resistance for the OUT terminal to prevent wrong operation of IC.
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RD151TS502US 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:PLL clock generator series
RD151TS502USE 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:PLL clock generator series
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