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参数资料
| 型号： | RD15LD74ATH0 |
| 元件分类： | 标准逻辑 |
| 英文描述： | SPECIALTY LOGIC CIRCUIT, PDSO20 |
| 封装： | 4.40 X 6.50 MM, 6.50 MM PITCH, PLASTIC, TSSOP-20 |
| 文件页数： | 9/12页 |
| 文件大小： | 168K |
| 代理商： | RD15LD74ATH0 |
RD15LD74AP, RD15LD74ANP, RD15LD74AT
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 4 of 9
Switching Characteristics
(Ta = –20 to +85
°C, CL = 30 pF, tr = tf =6 ns )
Ratings
Item
Symbol
VCC (V)
Min
Max
Unit
Conditions
3.3
± 0.3
—
15
Maximum clock
frequency
fmax
5.0
± 0.5
—
20
MHz
3.3
± 0.3
1.0
65
Propagation delay
time
tPLH
5.0
± 0.5
1.0
50
ns
CLK,
CLR to Y
3.3
± 0.3
1.0
60
Propagation delay
time
tPHL
5.0
± 0.5
1.0
45
ns
CLK to
Y
3.3
± 0.3
25
—
Setup time
tsu
5.0
± 0.5
20
—
ns
D to CLK
3.3
± 0.3
3
—
Hold time
th
5.0
± 0.5
3
—
ns
CLK to D
3.3
± 0.3
50
—
Pulse width
tW
5.0
± 0.5
40
—
ns
CLK,
CLR
3.3
± 0.3
—
30
Output rise time
tTLH
5.0
± 0.5
—
20
ns
Y
3.3
± 0.3
—
10
Output fall time
tTHL
5.0
± 0.5
—
5
ns
Y
Test Circuit
VCC
CLK
Zout = 50
Input
Palse generator
Note: 1. Input waveform : PRR = 1MHz, Duty Cycle = 50%, tr = 6ns, tf = 6ns
2. CL includes probe and jig capacitance.
CLR
Zout = 50
Input
Palse generator
CL = 30 pF
VT = 12V
Y
D
RL = 120
VCC
GND
Output
See
Function
Table
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