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参数资料
| 型号： | RD74LVC1G79WPE |
| 元件分类： | 锁存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA5 |
| 封装： | 0.40 MM PITCH, 0.40 MM HEIGHT, WCSP-5 |
| 文件页数： | 9/11页 |
| 文件大小： | 1973K |
| 代理商： | RD74LVC1G79WPE |
RD74LVC1G79
Rev.1.00 Feb 23, 2006 page 5 of 8
Switching Characteristics
VCC = 1.8
±0.15 V
Item
Symbol
Min
Typ
Max
Unit
Test conditions
FROM
(Input)
TO
(Output)
Maximum clock frequency
fmax
160
MHz
CL = 30 pF
Propagation delay time
tPLH, tPHL
4.4
9.9
ns
CL = 30 pF
CLK
Q
Setup time
tsu
2.2
ns
D
Hold time
th
0.3
ns
Pulse width
tw
2.5
ns
CLK “H” or “L”
VCC = 2.5
±0.2 V
Item
Symbol
Min
Typ
Max
Unit
Test conditions
FROM
(Input)
TO
(Output)
Maximum clock frequency
fmax
160
MHz
CL = 30 pF
Propagation delay time
tPLH, tPHL
2.3
7.0
ns
CL = 30 pF
CLK
Q
Setup time
tsu
1.4
ns
D
Hold time
th
0.4
ns
Pulse width
tw
2.5
ns
CLK “H” or “L”
VCC = 3.3
±0.3 V
Item
Symbol
Min
Typ
Max
Unit
Test conditions
FROM
(Input)
TO
(Output)
Maximum clock frequency
fmax
160
MHz
CL = 50 pF
Propagation delay time
tPLH, tPHL
2.0
5.0
ns
CL = 50 pF
CLK
Q
Setup time
tsu
1.3
ns
D
Hold time
th
1.0
ns
Pulse width
tw
2.5
ns
CLK “H” or “L”
VCC = 5.0
±0.5 V
Item
Symbol
Min
Typ
Max
Unit
Test conditions
FROM
(Input)
TO
(Output)
Maximum clock frequency
fmax
160
MHz
CL = 50 pF
Propagation delay time
tPLH, tPHL
1.3
4.5
ns
CL = 50 pF
CLK
Q
Setup time
tsu
1.2
ns
D
Hold time
th
0.5
ns
Pulse width
tw
2.5
ns
CLK “H” or “L”
Operating Characteristics
Ta = 25°C
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test Conditions
1.8
—
20
—
2.5
—
21
—
3.3
—
22
—
Power dissipation capacitance
CPD
5.0
—
26
—
pF
f = 10 MHz
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