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参数资料
| 型号： | RDA012M4MS-HD |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12 Bit 1.3 GS/s Master-Slave 4:1 MUXDAC |
| 中文描述： | 12位1.3 GS / s的主从4:1 MUXDAC |
| 文件页数： | 3/13页 |
| 文件大小： | 427K |
| 代理商： | RDA012M4MS-HD |
RDA012M4MS DATASHEET
DS_0017PB0-2805
Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.
The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 3 of 13
Electrical Specification
PARAMETER
ACCURACY
Differential Nonlinearity
Integral Nonlinearity
DYNAMIC PERFORMANCE
SYMBOL
CONDITIONS, NOTE
TEST LEVEL
MIN
TYP
MAX UNITS
DNL
INL
2
2
±2
±2.5
LSB
LSB
SFDR1
SFDR2
SFDR3
SNDR
FD
F
clk
= 800MHz , F
out
= 267MHz
F
clk
= 1000MHz , F
out
= 333MHz
F
clk
= 1300MHz , F
out
= 400MHz
1
1
1
56
53
50
dBc
dBc
dBc
dB
dB
Spurious Free Dynamic
Range
Signal Noise Ratio
Clock Feedthrough
ANALOG SIGNAL OUTPUT (OUTP, OUTN)
Full-scale Output Range
V
FSS
Single Ended, 50
Termination to
Ground
Single Ended, 50
Termination to
Ground (MIN=000h, MAX=FFFh)
Differential with 50
Termination to
Ground on each output
20%-80% with FSR output
20%-80% with FSR output
2
570
600
630
mV
p-p
Full-scale Output Range
V
FSRS
-650
0
mV
Full-scale output swing
V
FSD
2
1140
1200
1260
mV
p-p
Output current
Rise Time
Fall Time
Settling Time
CORE CLOCK INPUT (HCLKIP, HCLKIN)
Amplitude
Common Mode Voltage
Input Resistance
Input Capacitance
Maximum Frequency
Minimum Frequency
CLOCK INPUT (LCLKIP, LCLKIN)
Amplitude
Common Mode Voltage
Input Resistance
Maximum Frequency
Minimum Frequency
CLOCK OUPUT (LCLKOP, LCLKON)
Amplitude
Common Mode Voltage
Maximum Frequency
Minimum Frequency
DIGITAL INPUTS (A<0:11>, B<0:11>, C<0:11>, D<0:11>)
Input High Voltage
Input Low Voltage
Input Resistance
Setup Time
Hold Time
I
OUT
T
R,OUT
T
F,OUT
T
SETTL
3
12
mA
ps
ps
ps
V
CPP,HCLKI
V
CM,HCLKI
R
HCLKI
C
HCLKI
F
MAX,HCLKI
F
MIN,HCLKI
Differential ECL
1
1
3
3
3
400
-0.8
45
1300
600
-1.5
50
800
-2.0
55
1
mVpp
V
fF
MHz
MHz
V
CPP,LCLKI
V
CM,LCLKI
R
LCLKI
F
MAX,LCLKI
F
MIN,LCLKI
Differential LVDS
2
2
3
3
3
250
0.9
325
350
1.2
100
450
1.5
0.25
mVpp
mV
MHz
MHz
V
CPP,LCLKO
V
CM,LCLKO
F
MAX,LCLKO
F
MIN,LCLKO
2
2
3
3
250
0.9
325
350
1.2
450
1.5
0.25
mVpp
mV
MHz
MHz
V
IH
V
IL
R
DIN
t
ST,DTHCK
t
HL,DTHCK
From data input to LCLKO
From LCLKO to data input
2
2
3
3
0.9
-0.4
300
-50
VCC
0.4
V
V
ps
ps
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