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参数资料
| 型号： | RF3322 |
| 厂商： | RF MICRO DEVICES INC |
| 元件分类： | 衰减器 |
| 英文描述： | CABLE REVERSE PATH PROGRAMMABLE GAIN AMPLIFIER |
| 中文描述： | 5 MHz - 65 MHz RF/MICROWAVE NARROW BAND LOW POWER AMPLIFIER |
| 封装： | QSOP-20 |
| 文件页数： | 4/14页 |
| 文件大小： | 169K |
| 代理商： | RF3322 |
Preliminary
3-30
RF3322
Rev A2 010518
3
L
A
Serial Bus Block Diagram
Pin
1
2
Function
GND
VCC1
Description
Connect to ground.
Interface Schematic
This pin is connected to the supply voltage, and should be decoupled
as close to GND1 as possible.
Connect to ground.
3
4
5
6
GND
GND1
V IN+
V IN-
PGA RF ground.
Input pin. This should be externally AC-coupled to signal source.
Complementary input pin. This should be externally coupled to signal
source. For single-ended use, this pin should be AC-coupled to ground
through an impedance equivalent to the impedance driving V IN+.
Connect to ground.
7
8
9
10
11
12
GND
CS
SDA
SCLK
GND
SHDN
Serial bus enable.
Serial bus data input.
Serial bus clock input.
Connect to ground.
Ship shutdown pin. Forcing a logic low causes all circuits to switch off
and gain settings to be lost.
Not connected.
13
14
NC
RAMP
Turn-on time is controlled by an external capacitor between this pin and
ground.
Open collector output. Connect to V
CC
via balun primary.
Open collector output. Connect to V
CC
via balun primary.
Not connected.
15
16
17
18
V OUT-
V OUT+
NC
TXEN
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
This pin is connected to the supply voltage, and should be decoupled
as close to GND2 as possible.
Power amplifier bias ground.
19
VCC2
20
GND2
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D0
D1
D2
D3
D4
D5
D6
POR
CS
SDA
SCLK
D
CK
Q
CLR
D
CK
Q
CLR
D7
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