参数资料
型号: RFRXD0920-I/LQ
厂商: Microchip Technology
文件页数: 5/32页
文件大小: 0K
描述: MODULE RCVR 868/915MHZ ASK/FSK
产品变化通告: RFRXD0(4,9)20I/LQ Obsolescence 07/Mar/2012
标准包装: 250
频率: 800MHz ~ 930MHz
灵敏度: -106dBm
数据传输率 - 最大: 80 kbps
调制或协议: ASK,FM,FSK
应用: 家庭自动化,遥感,RKE
电流 - 接收: 9.2mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
rfRXD0420/0920
2.0
CIRCUIT DESCRIPTION
The PLL consists of a phase-frequency detector,
charge pump, voltage-controlled oscillator (VCO), and
This section gives a circuit description of the internal
circuitry of the rfRXD0420/0920 receiver. External
connections and components are given in the
APPLICATION CIRCUITS section.
fixed divide-by-16 (rfRXD0420) or divide-by-32
(rfRXD0920) divider. The rfRXD0420/0920 employs a
charge pump PLL that offers many advantages over
the classical voltage phase detector PLL: infinite pull-in
2.1
Bias Circuitry
range and zero steady state phase error. The charge
pump PLL allows the use of passive loop filters that are
Bias circuitry provides bandgap biasing and circuit
shutdown capabilities. The ENRX (Pin 28) modes are
summarized in Table 2-1. The ENRX pin is a CMOS
compatible input and is internally pulled down to Vss.
TABLE 2-1: BIAS CIRCUITRY CONTROL
lower cost and minimize noise. Charge pump PLLs
have reduced flicker noise thus limiting phase noise.
An external loop filter is connected to pin LF (Pin 29).
The loop filter controls the dynamic behavior of the
PLL, primarily lock time and spur levels. The applica-
tion determines the loop filter requirements.
ENRX (1)
0
Description
Standby mode
The VCO gain for the rfRXD0420/0920 receivers are
listed in Table 2-2.
1
Receiver enabled
TABLE 2-2:
PLL PARAMETERS
Note 1: ENRX has internal pull-down to Vss
Device
K VCO(1)
I CP(1)
Divider
2.2
Frequency Synthesizer
rfRXD0420
250 MHz/V at
433 MHz
60 μ A
16
The Phase-locked Loop (PLL) frequency synthesizer
rfRXD0920
300 MHz/V at
60 μ A
32
generates the Local Oscillator (LO) signal. It consists
of:
868 MHz
Note 1: Typical value
?
Crystal oscillator
?
?
Phase-frequency detector and charge pump
Voltage Controlled Oscillator (VCO)
The LF pin is illustrated in Figure 2-2.
?
Fixed feedback divider:
- rfRXD0420 = divide by 16
FIGURE 2-2:
BLOCK DIAGRAM OF LOOP
FILTER PIN
- rfRXD0920 = divide by 32
2.2.1
CRYSTAL OSCILLATOR
V DD
200 ?
The internal crystal oscillator is a Colpitts type oscilla-
LF
tor. It provides the reference frequency to the PLL. A
crystal is normally connected to the XTAL (Pin 26) and
ground. The internal capacitance of the crystal oscilla-
29
V SS
400 ?
4 pF
tor is 15 pF. Alternatively, a signal can be injected into
the XTAL pin from a signal source. The signal should
be AC coupled via a series capacitor at a level of
V SS
V SS
approximately 600 mV pp .
The XTAL pin is illustrated in Figure 2-1.
2.3
Low Noise Amplifier
The Low-Noise Amplifier (LNA) is a high-gain amplifier
FIGURE 2-1:
BLOCK DIAGRAM OF
XTAL PIN
whose primary purpose is to lower the overall noise
figure of the entire receiver thus enhancing the receiver
sensitivity. The LNA is an open-collector cascode
design. The benefits of a cascode design are:
XTAL
26
V DD
V SS
V DD
50 k ?
30 pF
30 pF
V DD
40 μ A
?
?
?
?
high gain with low noise
high-frequency
wide bandwidth
low effective input capacitance with stable input
impedance
? high output resistance
V SS
V SS
? high reverse isolation that provides improved
stability and reduces LO leakage
? 2003 Microchip Technology Inc.
Preliminary
DS70090A-page 5
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