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参数资料
| 型号： | RJ80530VZ733256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 733 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 15/101页 |
| 文件大小： | 2159K |
| 代理商： | RJ80530VZ733256 |
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Electrical Specifications
R
20
Mobile Intel
Celeron Processor (0.13 ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
Table 6. Recommended Resistors for Mobile Intel Celeron Processor Signals
Recommended
Resistor Value (
)
Mobile Intel Celeron Processor Signal
1, 2
10 pull-down
BREQ0#
3
14 pull-up
NCTRL
39 pull-up
TMS
39 pull-down
TCK
56.2 pull-up
PRDY#, RESET#
4
56.2 pull-down
RTTIMPEDP
110 pull-down
EDGECTRLP
150 pull-up
PICD[1:0], TDO
200-300 pull-up
PREQ#, TDI
500 pull-down
TRST#
1K pull-up
BSEL[1:0], TESTHI, VID[4:0], VTTPWRGD
1K pull-down
TESTLO
1.5k pull-up
FERR#, IERR#, PWRGOOD
3K pull-up
FLUSH#
Additional Pullup/Pulldown Resistor Recommendations
6
270 pull-up
SMI#
680 pull-up
STPCLK#
1.5k pull-up
A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI
NOTES:
1. The recommendations above are only for signals that are being used. These recommendations are maximum
values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should not violate the
chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not
being used.
2. Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if there
is too much undershoot.
3. A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
4. A 56.2
1% terminating resistor connected to VCCT is required.
5. The following signals are actively driven high by the ICH3-M component and do not need external pull up
resistors on ICH3-M based platforms: A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#.
6. These pull up recommendations apply to systems on which these signals are not actively pulled high such as
those utilizing the 82443MX chipset.
3.1.1
Power Sequencing Requirements
Unlike the Mobile Intel Celeron Processor (0.18 ), the Mobile Intel Celeron Processor (0.13 ) does
have specific power sequencing requirements. The power on sequencing and timings are shown in
Figure 15 and Table 31. Power down timing requirements are shown in Figure 16, Figure 17, and Table
31. The VCC power plane must not rise too fast. At least 200 sec (TR) must pass from the time that VCC
is at 10% of its nominal value until the time that VCC is at 90% of its nominal value. For more details,
please refer to the Intel Mobile Voltage Positioning -II (IMVP-II) Design Guide (contact your Field
Sales Representative).
3.1.2
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage
levels supported by the TAP interface, Intel recommends that the Mobile Intel Celeron Processor and the
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