参数资料
型号: RJ80536GE0362M
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 1860 MHz, MICROPROCESSOR, PBGA479
封装: FLIP CHIP, MICRO BGA-479
文件页数: 7/30页
文件大小: 887K
代理商: RJ80536GE0362M
Datasheet
15
Low Power Features
2.3
FSB Low Power Enhancements
The Pentium M Processor incorporates the following FSB low power enhancements:
Dynamic FSB Power Down
BPRI# control for address and control input buffers
Dynamic On Die Termination disabling
Low VCCP (I/O termination voltage)
The Pentium M Processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates them only
when data bus activity occurs, resulting in significant power savings with no performance impact.
BPRI# control also allows the processor address and control input buffers to be turned off when the
BPRI# signal is inactive. The On Die Termination on the processor FSB buffers is disabled when
the signals are driven low, resulting in additional power savings. The low I/O termination voltage is
on a dedicated voltage plane independent of the core voltage, enabling low
I/O switching power at all times.
2.4
Processor Power Status Indicator (PSI#) Signal
The Pentium M Processor incorporates the PSI# signal that is asserted when the processor is in a
low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and
deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator,
resulting in platform power savings and extended battery life. PSI# can also be used to simplify
voltage regulator designs since it removes the need for integrated 100
s timers required to mask
the PWRGOOD signal during Deeper Sleep transitions. It also helps loosen PWRGOOD
monitoring requirements in the Deeper Sleep state
§
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