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| 型号： | RJ80536NC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 3/68页 |
| 文件大小： | 863K |
| 代理商： | RJ80536NC0211M |
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Datasheet
11
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Celeron M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep
Sleep states for optimal power management. See Figure 1 for a visual representation of
the processor low-power states.
2.1.1
Normal State
This is the normal operating state for the processor.
2.1.2
AutoHALT Power-Down State
AutoHALT Power-Down is a low-power state entered when the processor executes the
HALT instruction. The processor will transition to the Normal state upon the occurrence
of SMI#,INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause
the processor to immediately initialize itself.
The system can generate a STPCLK# while the processor is in the AutoHALT Power-
Down state. When the system deasserts the STPCLK# interrupt, the processor will
return execution to the HALT state. While in AutoHALT Power-Down state, the processor
will process bus snoops and interrupts.
2.1.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor issued Stop-Grant Acknowledge
special bus cycle.
Figure 1.
Clock Control States
snoop
occurs
Stop
Grant
Normal
Sleep
HALT/
Grant
Snoop
Auto Halt
Deep
Sleep
STPCLK# asserted
SLP# asserted
SLP# deasserted
STPCLK# deasserted
snoop
serviced
HLT
instruction
snoop
serviced
snoop
occurs
DPSLP#
de-asserted
DPSLP#
asserted
STPCLK#
asserted
STPCLK#
deasserted
halt
break
V0001-04
Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
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相关代理商/技术参数 |
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