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参数资料
| 型号： | RM54ACT175VFA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 锁存器 |
| 英文描述： | ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 封装： | CERPACK-16 |
| 文件页数： | 1/12页 |
| 文件大小： | 207K |
| 代理商： | RM54ACT175VFA |
54AC175
54ACT175
Quad D Flip-Flop
General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The de-
vice is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D in-
puts is stored during the LOW-to-HIGH clock transition. Both
true and complemented outputs of each flip-flop are pro-
vided. A Master Reset input resets all flip-flops, independent
of the Clock or D inputs, when LOW.
Features
n Edge-triggered D-type inputs
n Buffered positive edge-triggered clock
n Asynchronous common reset
n True and complement output
n Outputs source/sink 24 mA
n ’ACT175 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC175: 5962-89552
— ’ACT175: 5962-89693
Logic Symbols
Pin Names
Description
D
0–D3
Data Inputs
CP
Clock Pulse Input
MR
Master Reset Input
Q
0–Q3
True Outputs
Q
0–Q3
Complement Outputs
Connection Diagrams
FACT is a registered trademark of Fairchild Semiconductor Corporation.
DS100278-1
IEEE/IEC
DS100278-2
Pin Assignment
for DIP and Flatpak
DS100278-3
Pin Assignment for LCC
DS100278-4
August 1998
54AC175
54ACT175
Quad
D
Flip-Flop
1998 National Semiconductor Corporation
DS100278
www.national.com
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