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| 型号： | RN80532KC0371M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1900 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | Interposer, Micro, PGA-603 |
| 文件页数： | 75/132页 |
| 文件大小： | 2316K |
| 代理商： | RN80532KC0371M |
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Intel Xeon Processor MP with up to 2MB L3 Cache
3-1
System Bus Signal Quality Specifications
System Bus Signal Quality
Specifications
3
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For
these reasons, it is crucial that the designer assure acceptable signal quality across all systematic
variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and all specifications are specified at the processor core (pad measurements).
Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all system bus AC timing specifications in
3.1
System Bus Clock (BCLK) Signal Quality
Specifications and Measurement Guidelines
Table 22 describes the signal quality specifications at the processor pads for the processor system
bus clock (BCLK) signals. Figure 20 describes the signal quality waveform for the system bus
clock at the processor pads.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 22. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes1
BCLK[1:0] Overshoot
N/A
0.30
V
BCLK[1:0] Undershoot
N/A
0.30
V
BCLK[1:0] Ringback Margin
0.20
N/A
V
BCLK[1:0] Threshold Region
N/A
0.10
V
2
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相关代理商/技术参数 |
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