参数资料
型号: RS5C321A-E1
厂商: RICOH COMPANY LTD
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO8
封装: 0.65 MM PITCH, SSOP-8
文件页数: 3/33页
文件大小: 286K
代理商: RS5C321A-E1
RS5C321A/B
7
FUNCTIONAL DESCRIPTION
1. Addressing
Address
Registers
Data *1
A3
A2
A1
A0
D3
D2
D1
D0
0
1-second counter
(BANK=0)
S8
S4
S2
S1
1
0
1
10-second counter
(BANK=0)
—*2
S40
S20
S10
2
0
1
0
1-minute counter
(BANK=0)
M8
M4
M2
M1
3
0
1
10-minute counter
(BANK=0)
M40
M20
M10
4
0
1
0
1-hour counter
(BANK=0)
H8
H4
H2
H1
5
0
1
0
1
10-hour counter
(BANK=0)
P/A, H20
H10
6
0
1
0
Day of the week counter
(BANK=0)
W4
W2
W1
7
0
1
Scratch register*8
(BANK=0, 1)
Scratch*8
8
1
0
1-day counter
(BANK=0)
D8
D4
D2
D1
9
1
0
1
10-day counter
(BANK=0)
D20
D10
A
1
0
1
0
1-month counter
(BANK=0)
MO8
MO4
MO2
MO1
32kHz clock pulse control register
(BANK=1)
CLEN*7
B
1
0
1
10-month counter
(BANK=0)
MO10
C
1
0
1-year counter
(BANK=0)
Y8
Y4
Y2
Y1
D
1
0
1
10-year counter
(BANK=0)
Y80
Y40
Y20
Y10
E
1
0
Control register 1
(BANK=0, 1)
WTEN
*6
/XSTP
*4 ADJ/BSY *3
F
1
Control register 2
(BANK=0, 1)
12/24
BANK *5
TEST *6
*1) All the listed data can be read and written.
*2) The “—” mark indicates data which can be read only and set to “0” when read.
*3) The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation.
*4) The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation.
*5) The clock/calendar counter and the 32kHz clock pulse control register can be selected when the BANK=0 and BANK=1 respectively. To designate
the BANK is unnecessary for scratch register and control register 1/2.
*6) The WTEN bit and TEST bit are set to “1” when CE is “L”.
*7) The CLEN bit is set to 0, when initial power-on or XSTP is set to 1.
*8) Data may be written and read into/from the Scratch register, which actually is not used.
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