
RT9183
Preliminary
11
DS9183-02 December 2003
www.richtek.com
The final operating junction temperature for any set of
conditions can be estimated by the following thermal
equation:
PD (MAX) = ( TJ (MAX)
TA ) / θθθθθJA
Where TJ (MAX) is the maximum junction temperature of
the die (125
°C) and TA is the maximum ambient
temperature. The junction to ambient thermal resistance
(
θJA) for SOP-8 package at recommended minimum
footprint is 42
°C/W, 40°C/W for SOT-223 package and
25
°C/W for TO-263 package (θJA is layout dependent).
Visit our website in which “Recommended Footprints for
Soldering Surface Mount Packages” for detail.
PCB LAYOUT
Good board layout practices must be used or instability
can be induced because of ground loops and voltage drops.
The input and output capacitors MUST be directly
connected to the input, output, and ground pins of the
device using traces which have no other currents flowing
through them.
The best way to do this is to layout CIN and COUT near the
device with short traces to the VIN, VOUT, and ground pins.
The regulator ground pin should be connected to the
external circuit ground so that the regulator and its
capacitors have a“ single point ground” .
It should be noted that stability problems have been seen
in applications where “ vias ” to an internal ground plane
were used at the ground points of the device and the input
and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing
through the ground plane. Using a single point ground
technique for the regulator and it's capacitors fixed the
problem. Since high current flows through the traces going
into VIN and coming from VOUT, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in series
with the input and output capacitors.
Optimum performance can only be achieved when the
device is mounted on a PC board according to the diagram
below:
SOP-8 Board Layout
GND
ADJ
GND
VIN
VOUT
EN
+
+ + + +
++++
ADJUSTABLE OPERATION
The adjustable version of the RT9183 has an output voltage
range of 0.8V to 4.5V. The output voltage is set by the
ratio of two external resistors as shown in Figure 2. The
value of R2 should be less than 80k to maintain regulation.
In critical applications, small voltage drop is caused by
the resistance (RT) of PC traces between the ground pin of
the device and the return pin of R2 (See Figure 4 shown on
next page). Note that the voltage drop across the external
PC trace will add to the output voltage of the device.
Optimum regulation will be obtained at the point where
the return pin of R2 is connected to the ground pin of the
device directly.
Referring to Figure 3 the fixed voltage versions for both
SOP-8 and TO-263-5 packages, the ADJ pin is the input
to the error amplifier and MUST be tied the ground pin of
the device directly otherwise it will be in the unstable state
if the pin voltage more than 0.1V with respect to the ground
pin itself.
Figure 4. Return Pin of External Resistor Connection
Enable
VOUT
VIN
VOUT
EN
GND
ADJ
RT9183
VIN
R1
R2
C2
10uF
C1
10uF
(SOP-8 & TO-263-5)
C3
0.1uF
RT