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参数资料
| 型号： | RTC-9701JEB-3 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO20 |
| 封装： | VSOJ-20 |
| 文件页数： | 2/3页 |
| 文件大小： | 261K |
| 代理商： | RTC-9701JEB-3 |
79
Real time clock module
80
Real time clock module
Register table
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
SEC
–
S 40
S 20
S 10
S 8
S 4
S 2
S 1
1
MIN
–
M 40
M 20
M 10
M 8
M 4
M 2
M 1
2
HOUR
–
H 20
H 10
H 8
H 4
H 2
H 1
3
WEEK
–
W 6
W 5
W 4
W 3
W 2
W 1
W 0
4
DAY
–
D 20
D 10
D 8
D 4
D 2
D 1
5
MONTH
–
C 10
C 8
C 4
C 2
C 1
6
YEAR
Y 80
Y 40
Y 20
Y 10
Y 8
Y 4
Y 2
Y 1
7
Y100
0
1
0
8
MIN Alarm
AE
MA 40
MA 20
MA 10
MA 8
MA 4
MA 2
MA 1
9
HOUR Alarm
AE
–
HA 20
HA 10
HA 8
HA 4
HA 2
HA 1
A
WEEK Alarm
AE
WA 6
WA 5
WA 4
WA 3
WA 2
WA 1
WA 0
DAY Alarm
–
DA 20
DA 10
DA 8
DA 4
DA 2
DA 1
B
Reserved
C
Interval Timer
TDUTY
CT6
CT 5
CT 4
CT3
CT 2
CT 1
CT 0
D
Extension Register
TEST
WADA
UDUTY
USEL
–
TSEL 1
TSEL 0
E
Flag Register
VLF2
–
UF
TF
AF
EXF
VLF
–
F
Control Register
–
UIE
TIE
AIE
EXIE
VLIE
–
AC characteristics (GND=0 V, VDD=2.7Vto3.6V,VDD2=1.8Vto5.5V, Ta=-40°Cto+85°C)
Item
Symbol Condition
Min. Typ. Max. Unit
CLK clock cycle
tCLK Vth = 0.5 VDD
500
ns
CLK H Pulse Width
tWH Vth = 0.5 VDD
230
ns
CLK L Pulse Width
tWL Vth = 0.5 VDD
230
ns
CE setup time
tCS
110
ns
CE hold time
tCH
170
ns
Write data setup time tDS
150
ns
Write data hold time
tDH
150
ns
Read data delay time
tRD CL = 65pF ± 10pF
240 ns
DO output mode switching time tZR CL = 65pF ± 10pF 170
ns
DO output disable time
tRZ CL=65pF±10pFRL=10kΩ
240 ns
Ready setup time
tRDY
65
ns
Rise and fall time
tRF VDD: 20% to 80 %
30
ns
Carry busy
tcarry Xtal = 32.768kHz
7.8125 ns
FOUT duty ratio
tW/t Vth = 1/2VDD VDD= 3.0V 40
50
60
%
Block diagram
BUS
INTERFACE
CIRCUIT
E2PROM
256 x 16 bit
FOUT CONTROLLER
INTERRUPTS
CONTROLLER
DIVIDER
FOUT
TIRQ
AIRQ
CLK
GND
VEX
VDD
FOE
VLF
CE
DO
DI
TIMER REGISTER
ALARM REGISTER
CONTROL REGISTER
CLOCK and CALENDER
OSC
RTC
32.768 kHz
Control Line
VDD2
VI VO
Timing chart
tCS
tCR
tCH
tWH
tWL
tDH
tDS
tRZ
tZZ
tZR
tRD
tRZ
Hi-Z
tRDY
m3
m2
a0
d7
d6
d5
d0
d7
d6
d5
d0
tZR
Busy
Ready
tr
tf
tCLK
VTH
CE
CLK
DI
DO
Read
Write
DI
DO
80%
20%
EEPROM Table
Segment
Address
Data
dF
dE
dD
dC
dB
dA
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
0
00
User Memory
4 kbit (256 x 16 bit)
…
FF
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