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参数资料
| 型号： | RVPXA272FC5520 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 520 MHz, RISC PROCESSOR, PBGA336 |
| 封装： | 14 X 14 MM, 1.45 MM PITCH, LEAD FREE, CSP-336 |
| 文件页数： | 26/44页 |
| 文件大小： | 1302K |
| 代理商： | RVPXA272FC5520 |
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Electrical Specifications
32
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
4.7.2
Hardware Reset Timing
The timing sequences shown in hardware reset timing for hardware reset assumes stable power
supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings
indicated in Section 4.7.1, “Power-On Timing” on page 30.
4.7.3
Watchdog Reset Timing
Watchdog reset is an internally generated reset and therefore has no external pin dependencies. The
nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for tDHW_OUT.
4.7.4
GPIO Reset Timing
GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies
based on the frequency of clock selected, and if the clocks and power manager is in the frequency
change sequence when GPIO reset is asserted (see Section 4.6.1, “32.768-kHz Oscillator
Specifications” on page 28.) Figure 5, “GPIO Reset Timing” on page 33 shows the possible timing
of GPIO reset.
Figure 4. Hardware Reset Timing
Table 16. Hardware Reset Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tDHW_NRESET
Minimum assertion time of nRESET
0.001
ms
tDHW_OUT_A
Delay between nRESET asserted and
nRESET_OUT asserted
0
0.001
ms
tDHW_OUT
Delay between nRESET de-asserted and
nRESET_OUT de-asserted
18.1
18.2
ms
tDHW_NCS0
Delay between nReset_Out de-asserted
and nCS0 asserted
400
—
420
ns
nRESET
nRESET_OUT
t
DHW_NRESET
t
DHW_OUT
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted
or the Cotulla will enter Sleep Mode
t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
de-asserted or the PXA255 processor enters sleep mode.
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