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参数资料
| 型号： | RX-4591CF |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封装： | SON-10 |
| 文件页数： | 3/19页 |
| 文件大小： | 256K |
| 代理商： | RX-4591CF |
RX - 4591 CF
Page - 8
MQ - 402 - 01
8.2.4. Control register and flag register (between Reg-D and Reg-F)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D
Extension register TEST WADA USEL
TE
TSEL1 TSEL0
E
Flag register
VDET
VLOW
UF
TF
AF
ICNT
VLF
PON
F
Control register
TEST
UIE
TIE
AIE
STOP RESET
TEST bit: This bit is used by manufacture for testing.
Be sure to set this bit to "0". Be careful not to set this bit to "1" when writing to other bits of Reg-D.
When CE pin goes to L, TEST is cleared .
WADA bit (WEEK Alarm / DAY Alarm)
This bit sets either the WEEK alarm or the DAY alarm. When this bit is 0, the Reg-A is re-assigned to the
WEEK alarm register. And when this bit is 1, the Reg-A is re-assigned to the DAY alarm register.
USEL bit (Update Interrupt Select)
Specify the occurrence timing of time update interrupt.
[Selection of timing for time update interrupt]
USEL
Timing
Auto recovery time
0
Update in seconds
7.813 ms
1
Update in minutes
7.813 ms
TE bit (Timer Enable)
When the TE bit is 0, The presetable counter loads the written data to the timer counter (It is initial value. ),
and then stops the count down. And when the TE bit is 1, count down starts.
VDET ( Voltage Detect )
When power supply is higher than VDET voltage, this bit shows 0. And when power supply is lower than
VDETvoltage, this bit shows 1. But in this case, this bit continues keeping 1 till it is cleared by 0.
This bit is not affected by another bits ( STOP, RESET ).
VLOW ( Voltage Low )
When power supply is higher than VLOW voltage, this bit shows 0. And when power supply is lower than
VLOW voltage, this bit shows 1. But in this case, this bit continues keeping 1 till it is cleared by 0.
This bit is not affected by another bits ( STOP, RESET ).
AF bit, TF bit, and UF bit (Alarm Flag, Timer Flag, Update Flag)
When the alarm occurs , the AF bit is set to 1. When the data is just zero, the TF (Timer Flag) of Reg-E is set
to 1. At the end of time update, the UF bit is set. These data 1 is retained until writing over them with 0. You
cannot write "1" over these bits.
AIE bit, TIE bit, and UIE bit (Alarm, Timer, Update Interrupt Enable)
These bits control whether or not to generate interrupt signal from IRQpin, when alarm, timer, or time update
interrupt event occurs. AIE corresponds to alarm interrupt, TIE corresponds to timer interrupt, and UIE
corresponds to time update interrupt.
ICNT ( Invalid Counter Data )
When crystal oscillation is stopped by for example down of supply voltage, this bit shows 1.
But in this case, this bit continues keeping 1 till it is cleared by 0.
This bit is not affected by another bits ( STOP, RESET ).
VLF (Voltage Low Flag)
This bit shows the logic sum of each bit ( VLOW, ICNT, PON ). In this case, this bit continues keeping 1 till it
is cleared by 0. This bit is not affected by another bits ( STOP, RESET ).
PON bit ( Power On Reset )
When the initial power-up occurs, or device returns from a blackout or such as, this bit shows 1.
And this case, this bit continues keeping 1 till it is cleared by 0.
This bit is not affected by another bits ( STOP, RESET ).
STOP bit
When this bit is set to "1", the operation of counting up the seconds in the Clock & Calendar circuitry is
stopped, which stops the clock. When this bit is set to "0", the clock resumes its operation.
RESET bit
When this bit is set 1, clock update was stop and clock data (except seconds digits) is reset for 00 year
January 1day Sunday 00hour 00minutes. When CE terminal turned into L, this bit is cleared automatically.
After using the RESET function, set the all clock and calendar data.
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