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参数资料
| 型号： | S-812C38AUA-C2ST2U |
| 元件分类： | 固定正电压单路输出LDO稳压器 |
| 英文描述： | 3.8 V FIXED POSITIVE LDO REGULATOR, 0.35 V DROPOUT, PSSO3 |
| 封装： | HALOGEN FREE AND LEAD FREE, SOT-89, 3 PIN |
| 文件页数： | 9/39页 |
| 文件大小： | 690K |
| 代理商： | S-812C38AUA-C2ST2U |
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PRELIMINARY DATE: 11/13/01
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To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given
DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 9 * 15.6us (140.4us). This maximum absolute interval is short
enough to allow for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles,
without allowing too much drift in tAC between updates.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is
disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically
enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be
issued). Input signals except CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR
because time is required for the completion of any internal refresh in progress. A simple algorithm for
meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other
command.
OPERATIONS
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank
must be “opened.” This is accomplished by the ACTIVE command, which selects both the bank and the row
to be activated.
The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A10 selects the
row. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this
command is issued, Read or Write operation can be executed.
After opening a row, a READ or WRITE command may be issued to that row, subject to the tRCD
specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE
commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which
results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE
commands to different banks is defined by tRRD.
相关PDF资料 |
PDF描述 |
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| S-812C38BMC-C4ST2U | 3.8 V FIXED POSITIVE LDO REGULATOR, 0.35 V DROPOUT, PDSO5 |
| S-812C38BPI-C4STFU | 3.8 V FIXED POSITIVE LDO REGULATOR, 0.35 V DROPOUT, PDSO6 |
| S-814A49AMC-BDNT2U | 4.9 V FIXED POSITIVE LDO REGULATOR, 0.22 V DROPOUT, PDSO5 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S-812C38AY-B | 功能描述:低压差稳压器 - LDO 3.8V 1.0uA 2.0% RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| S-812C38AY-B2-U | 功能描述:低压差稳压器 - LDO 3.8V 1.0uA 2.0% RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| S-812C38AY-B-G | 制造商:Seiko Instruments Inc (SII) 功能描述:IC REG LDO 3.8V 0.05A TO92-3 |
| S-812C38AY-X | 制造商:SII 制造商全称:Seiko Instruments Inc 功能描述:HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR |
| S-812C38AY-X-G | 制造商:SII 制造商全称:Seiko Instruments Inc 功能描述:HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR |
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