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参数资料
| 型号： | S-812C47AY-B-G |
| 元件分类： | 固定正电压单路输出LDO稳压器 |
| 英文描述： | 4.7 V FIXED POSITIVE LDO REGULATOR, 0.27 V DROPOUT, PBCY3 |
| 封装： | LEAD FREE, TO-92, 3 PIN |
| 文件页数： | 39/39页 |
| 文件大小： | 690K |
| 代理商： | S-812C47AY-B-G |
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W946432AD
9
FUNCTIONAL DESCRIPTION
The W946432AD is a high speed CMOS, dynamic random access memory containing 67,108,864 bits. The
W946432AD is internally configured as a quad bank DRAM.
The W946432AD uses a double data rate architecture to achieve high speed operation. The double data rate
architecture is essentially a 32 prefetch architecture, with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the W946432AD consists of a single 32bit
wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32bit wide, one half
clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A10 select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide etailed
information covering device initialization, register definition, command descriptions and device operation.
INITIALIZATION
W986432AD must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and
finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch up, which may
cause permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be
nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied.
CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an
LVCMOS LOW level on CKE during power up is required to guarantee that the DQ and DQS outputs will be
in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay
prior to applying an executable command.
Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied.
Next a MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the
DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL,
and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read
command. A PRECHARGE ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER
SET command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating
parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready
for normal operation.
相关PDF资料 |
PDF描述 |
|---|---|
| S-812C47AY-T-G | 4.7 V FIXED POSITIVE LDO REGULATOR, 0.27 V DROPOUT, PBCY3 |
| S-812C47AY-Z-G | 4.7 V FIXED POSITIVE LDO REGULATOR, 0.27 V DROPOUT, PBCY3 |
| S-812C47BMC-C5BT2G | 4.7 V FIXED POSITIVE LDO REGULATOR, 0.27 V DROPOUT, PDSO5 |
| S-812C52AMC-C3GT2G | 5.2 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PDSO5 |
| S-812C52AUA-C3GT2G | 5.2 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PSSO3 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S-812C47AY-X | 制造商:SII 制造商全称:Seiko Instruments Inc 功能描述:HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR |
| S-812C47AY-X-G | 制造商:SII 制造商全称:Seiko Instruments Inc 功能描述:HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR |
| S-812C47BMC-C5BT2G | 功能描述:低压差稳压器 - LDO Linear LDO Reg 1.0uA Iq 75mA Iout ON/OFF RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| S-812C47BPI-C5BTFG | 功能描述:低压差稳压器 - LDO Linear LDO reg 1.0uA Iq 75mA Iout ON/OFF RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| S-812C48AMC-C3C-T2 | 功能描述:低压差稳压器 - LDO 4.8V 1.0uA 2.0% RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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