参数资料
型号: S-T111B51MC-OHKTFU
元件分类: 固定正电压单路输出LDO稳压器
英文描述: 5.1 V FIXED POSITIVE LDO REGULATOR, 0.26 V DROPOUT, PDSO5
封装: HALOGEN FREE AND LEAD FREE, SOT-23, 5 PIN
文件页数: 22/23页
文件大小: 225K
代理商: S-T111B51MC-OHKTFU
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-T111 Series
Rev.3.0_00
Seiko Instruments Inc.
8
Standard Circuit
ON/OFF
VSS
VOUT
VIN
CIN
*1
CL
*2
Input
Output
GND
Single GND
*1. CIN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.1
μF or more can be used for C
L.
Figure
9
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (CIN):
0.1
μF or more
Output capacitor (CL):
0.1
μF or more
ESR of output capacitor:
10
Ω or less
Caution A general series regulator may oscillate, depending on the external components selected.
Check that no oscillation occurs with the application using the above capacitor.
Selection of Input and Output Capacitors (CIN, CL)
The S-T111 Series requires an output capacitor between the VOUT and VSS pins for phase compensation.
Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1
μF or more in the entire
temperature range.
However, when using an OS capacitor, tantalum capacitor, or aluminum electrolytic
capacitor, a ceramic capacitor with a capacitance of 0.1
μF or more and an ESR of 10 Ω or less is required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor.
The required capacitance of the input capacitor differs depending on the application.
The recommended value for an application is 1.0
μF or more for C
IN and 0.47 μF or more for CL; however,
when selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature
characteristics, on the actual device.
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