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参数资料
型号： S1C88862F0A0100
元件分类： 微控制器/微处理器
英文描述： MICROCONTROLLER, PQFP128
封装： PLASTIC, QFP-128
文件页数： 4/160页
文件大小： 1244K
代理商： S1C88862F0A0100
S1C88832/88862 TECHNICAL MANUAL
EPSON
93
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller)
Fig. 5.11.4.3
Drive waveform for 1/8 duty
5.11.5 Display memory
The S1C88832 has a built-in 402-byte display
memory. The S1C88862 has a built-in 342-byte
display memory. The display memory is allocated
to address F800H–FD42H (including unavailable
areas) and the correspondence between the
memory bits and common/segment terminal is
changed according to the selection status of the
following items.
(1) Drive duty (1/32, 1/16 or 1/8 duty)
(2) Dot font (5
× 8 or 5 × 5 dots)
When 1/16 or 1/8 duty is selected for drive duty,
two-screen memory can be secured, and the two
screens can be switched by the display memory
area selection register DSPAR. When "0" is written
to DSPAR, display area 0 is selected and when "1" is
written, display area 1 is selected.
Furthermore, memory allocation for 5
× 8 dots and
5
× 5 dots can be selected in order to easily display
5
× 5-dot font characters on the LCD panel.
This selection can be done by the dot font selection
register DTFNT: when "0" is written to DTFNT, 5
×
8 dots is selected and when "1" is written, 5
× 5 dots
is selected.
The correspondence between the display memory
bits set according to the drive duty and font size,
and the common/segment terminals are shown in
Figures 5.11.5.1–5.11.5.6.
When "1" is written to the display memory bit
corresponding to the dot on the LCD panel, the dot
goes ON and when "0" is written, it goes OFF. Since
display memory is designed to permit reading/
writing, it can be controlled in bit units by logical
operation instructions and other means (read,
modify and write instruction)s.
The display memory bits that have not been
assigned can be used as general purpose RAM with
read/write capabilities. Even when external
memory has expanded into the display memory
area, this area is not released to external memory.
Access to this area is always via display memory.
COM0
1
2
3
4
5
6
7
SEG0
1
2
3
4
VDD
VSS
VC5
VC4
VC3
VC2
VC1
VSS
7
3
2
1
0
7
3
2
1
0
FR
COM0
COM1
COM2
SEG0
SEG1
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS (GND)
VC5
VC4
VC3
VC2
VC1
VSS (GND)
COM0–SEG0
COM0–SEG1
4
6
4
6
55
-VC1
-VC2
-VC3
-VC4
-VC5
-VC1
-VC2
-VC3
-VC4
-VC5
64 Hz
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