参数资料
型号: S1D13503F00A
元件分类: 显示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封装: QFP-100
文件页数: 4/20页
文件大小: 144K
代理商: S1D13503F00A
12
S1D13503 Series
Display Memory Interface
LCD Interface
Pin Name
Type
F00A
Pin No.
F01A
Pin No.
D00A
Pad No.
Driver
Descr iption
VD0–VD15
I/O
44–51,
54–61
41–48,
51–58
54–55,
57–61,
64,
68–75
TS1D2 These pins are connected to the display memory data bus.
For 16-bit interface, VD0–VD7 are connected to the display
memory data bus of even byte addresses and VD8–VD15 are
connected to the display memory data bus of odd byte
addresses. The output drivers of these pins are placed in a high
impedance state when RESET is high. On the falling edge of
RESET, the values of VD0–VD15 are latched into the chip to
configure various hardware options(see Table “Summary of
Power On/Reset Options” on page 13).
VA0–VA15
O
33–43,
62–66
30–40,
59–63
38–40,
42–43,
45–46,
48–49,
51–52,
77–81
CO1
These pins are connected to the display memory address bus.
VCS1#
O
69
66
84
CO1
Active low chip-select output to the second or odd byte address
SRAM. See Display Memory Interface section for details.
VCS0#
O
68
65
83
CO1
Active low chip-select output to the first or even byte address
SRAM. See Display Memory Interface section for details.
Active low output used for writing data to the display memory.
This pin is connected to the WE# input of the SRAMs.
Active low output to enable reading of data from the display
memory. This pin is connected to the OE# input of the SRAMs.
VWE#
O
67
64
82
CO1
VOE#
O
83
80
102
CO1
Pin Name
FPDI-1 TM
Pin Name #1
Type
F00A
Pin No.
F01A
Pin No.
D00A
Pad No.
Driver
Descr iption
UD3–UD0
LD3–LD 0
UD3–UD0
LD3–LD 0
O
70–73,
74–77
67–70,
71–74
86–89,
90–93
CO3S Panel display data bus. The data format depends
on the specific panel connected. For 4-bit single
panels, LD3–LD0 are driven low (0 state).
XSCL
FPSHIFT
O
81
78
100
CO3
LP
FPLINE
O
79
76
96
CO3
WF/
XSCL2
MOD
FPSHIFT2
O
80
77
97
CO3 For format 1 of 8-bit single color panels this is the
second shift clock.
For all other modes, this is the LCD backplane
BIAS signal. This output toggles once every frame,
or as programmed in AUX[05] bits 7–2.
YD
FPFRAME
O
78
75
94
CO3 Vertical scanning start pulse. A logic ‘1’ on this
signal, sampled by the LCD module on the falling
edge of LP, is used by the panel Y driver (row
driver) to indicate the start of the vertical frame.
LCDENB
O
82
79
101
CO2 LCD enable signal output. It can be used externally
to turn off the panel supply voltage and backlight.
Display data latch clock. The falling edge of this
signal is used to latch a row of display data in the
LCD X-drivers and to turn on the Y driver (row driver).
Display data shift clock. Data is shifted into the
LCD X-drivers on the falling edge of this signal.
Power Supply
Pin Name
Type
F00A
Pin No.
F01A
Pin No.
D00A
Pad No.
Driver
Descr iption
VDD
P
3, 53
50, 100
3, 67
P
Voltage supply..
VSS
P
2, 52
49, 99
1, 65
P
Voltage ground.
Pin Name
Type
F00A
Pin No.
F01A
Pin No.
D00A
Pad No.
Driver
Descr iption
OSC1
I
9 2
92
115
This pin, along with OSC2, is the 2-terminal crystal interface
when using a 2-terminal crystal as the clock input. If an external
oscillator is used as a clock source, then this pin is the clock input.
OSC2
O
93
116
This pin, along with OSC1, is the 2-terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator
is used as a clock source this pin should be left unconnected.
#1: VESA Flat Panel Display Interface Standard (FPDI-1TM)
Clock Inputs
相关PDF资料
PDF描述
S1DGPC SLIDE SWITCH, SPDT, LATCHED, 0.05A, 48VDC, THROUGH HOLE-STRAIGHT
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