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参数资料
| 型号： | S25FL004D |
| 厂商： | Spansion Inc. |
| 英文描述： | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| 中文描述： | 4兆位的CMOS闪存3.0伏，50赫兹的SPI总线接口 |
| 文件页数： | 7/36页 |
| 文件大小： | 724K |
| 代理商： | S25FL004D |
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June 28, 2004 S25FL004D_00A0
S25FL Family (Serial Peripheral Interface) S25FL004D
15
Ad va nc e
In forma t i o n
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be
read. The Status Register may be read at any time, even while a Program, Erase,
or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress (WIP) bit before
sending a new instruction to the device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 6.
Figure 6. Read Status Register (RDSR) Instruction Sequence
Figure 7. Status Register Format
The status and control bits of the Status Register are as follows:
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunc-
tion with the Write Protect (W#) signal. The Status Register Write Disable
(SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hard-
ware Protected mode (when the Status Register Write Disable (SRWD) bit is set
to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile.
They define the size of the area to be software protected against Program and
Erase instructions. These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 1) becomes protected against
Page Program (PP), and Sector Erase (SE) instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the Hardware Protected mode has not
Instruction
High Impedance
MSB
Status Register Out
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7 6
5 4 3 2 10
7 6 5 4 3 2 1 0 7
SO
SI
SCK
CS#
Status Register
Write Disable
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
SRWD
0
BP2
BP1
BP0
WEL
WIP
b7
b0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S25FL004D0FMFI | 制造商:Spansion 功能描述: |
| S25FL004D0LMAI011 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMAI013 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI011 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI013 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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