参数资料
型号: S29AL008D90MFN011
厂商: SPANSION LLC
元件分类: PROM
英文描述: 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
中文描述: 512K X 16 FLASH 3V PROM, 90 ns, PDSO44
封装: LEAD FREE, MO-180AAA, SOP-44
文件页数: 14/52页
文件大小: 2004K
代理商: S29AL008D90MFN011
February 27, 2009 S29AL008D_00_A11
S29AL008D
21
Data
She e t
7.12
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 8.1 on page 26 for command definitions). In addition, the following
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during VCC power-up and power-down transitions, or from system
noise.
7.12.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
7.12.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
7.12.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
7.12.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
8.
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 8.1 on page 26 defines the valid register command sequences. Writing incorrect address
and data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC
8.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/
Erase Resume Commands on page 25 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See Reset Command on page 22.
Operations on page 36 provides the read parameters, and Figure 15.1 on page 36 shows the timing diagram.
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