参数资料
型号: S29GL032A10TFIR10
厂商: SPANSION LLC
元件分类: PROM
英文描述: 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY
中文描述: 2M X 16 FLASH 3V PROM, 100 ns, PDSO56
封装: LEAD FREE, MO-142EC, TSOP-56
文件页数: 17/95页
文件大小: 3585K
代理商: S29GL032A10TFIR10
24
S29GL-A
S29GL-A_00_A12 May 21, 2008
Da ta
Sh e e t
7.3.1
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. See
Write Buffer on page 24 for more information.
7.3.2
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce
the time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC or ACC pin, depending on model
number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for
operations other than accelerated programming, or device damage may result. WP# contains an internal pull-
up; when unconnected, WP# is at VIH.
7.3.3
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 40 and Autoselect
Command Sequence on page 53 for more information.
7.4
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to DC Characteristics on page 70 for the standby current specification.
7.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to DC
Characteristics on page 70 for the automatic sleep mode current specification.
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