参数资料
型号: S29GL032M10BFIR10
厂商: SPANSION LLC
元件分类: PROM
英文描述: MirrorBit Flash Family
中文描述: 2M X 16 FLASH 3V PROM, 100 ns, PBGA64
封装: 13 X 11 MM, LEAD FREE, FORTIFIED BGA-64
文件页数: 14/158页
文件大小: 4695K
代理商: S29GL032M10BFIR10
110
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B1_E August 4, 2004
Data she e t
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the
address of the sector to be erased, and the sector erase command. Table 35 and Table 36 shows the address and
data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automati-
cally programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, ad-
ditional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these
additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to the read mode. Note that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when an erase operation is in progress. The system must rewrite the command sequence
and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector
Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no
longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the
erasing sector. Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the
sector erase command sequence should be reinitiated once the device has returned to reading array data, to en-
sure data integrity.
6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and 18 section for timing diagrams.
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