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参数资料
| 型号： | S29GL032M10BFIR12 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 2M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| 封装： | 13 X 11 MM, LEAD FREE, FORTIFIED BGA-64 |
| 文件页数： | 71/158页 |
| 文件大小： | 4695K |
| 代理商： | S29GL032M10BFIR12 |
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S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B1_E August 4, 2004
Data she e t
General Description
The S29GL256/128/064/032M family of devices are 3.0 V single power Flash memory manufactured using 0.23
um MirrorBit technology. The S29GL256M is a 256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The
S29GL128M is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The S29GL064M is a 64 Mbit, or-
ganized as 4,194,304 words or 8,388,608 bytes. The S29GL032M is a 32 Mbit, organized as 2,097,152 words or
4,194,304 bytes. Depending on the model number, the devices have an 8-bit wide data bus only, 16-bit wide data
bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The
devices can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128M, S29GL064M, S29GL032M) or 100 ns (S29GL256M) are available. Note
that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and
the Ordering Information sections. Package offerings include 40-pin TSOP, 48-pin TSOP, 56-pin TSOP, 48-ball fine-
pitch BGA, 63-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model number. Each device has sepa-
rate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC
input, a high-voltage accelerated program (ACC) feature provides shorter programming times through in-
creased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com-
mands are written to the device using standard microprocessor write timing. Write cycles also internally latch
addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation
has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the
Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an
Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data
instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations dur-
ing power transitions. The hardware sector protection feature disables both program and erase operations in any
combination of sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector
to read or program any other sector and then complete the erase operation. The Program Suspend/Program
Resume feature enables the host system to pause a program operation in a given sector to read any other sector
and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus
also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and
RESET#, or when addresses have been stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin
or WP# pin, depending on model number. The protected sector will still be protected even during accelerated
programming.
The SecSi (Secured Silicon) Sector provides a 128-word/256-byte area for code or data that can be perma-
nently protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector
simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
相关PDF资料 |
PDF描述 |
|---|---|
| S29GL032M10BFIR13 | MirrorBit Flash Family |
| S29GL032M10BFIR30 | T528 Series - I, M, Z Case Sizes - Face Down Termination Tantalum Surface Mount Capacitor; Capacitance [nom]: 220uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Tantalum, Solid; ESR: 12mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-17; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 1.7mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 1,000; Features: Face Down Termination |
| S29GL032M10FAIR22 | MirrorBit Flash Family |
| S29GL032M10FAIR23 | MirrorBit Flash Family |
| S29GL032M10FAIR30 | MirrorBit Flash Family |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29GL032M10BFIR13 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL032M10BFIR20 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BFIR22 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BFIR23 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BFIR30 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
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